LabVIEW FPGA Onboard Clock Access for Spartan 3E Starter Board

[troy.perales]

Is there anyway to access the onboard 50 MHz clock of the Spartan 3E Starter Board in a VI block diagram?

I am trying to tie the clock to an I/O pin; however, I can only get a 25 MHz pulse at best, since the Single Cycle Loop only executes on a full cycle and I can only negate my previous output for the time of that pulse instead of matching the clock.

I've tried created an HDL interface node, but to no avail.

Before I make any more attempts, is this even possible? If so, any suggestions?

Thanks and regards.

[troy.perales]

Maybe I should rephrase my question...

Is there any way to tie the onboard clock (50 MHz) directly to an I/O pin in LabVIEW FPGA?

[RyanB]

You are correct, with a 50MHz Single-Cycle Timed Loop (SCTL), you can generate a 25MHz clock to your digital output pin (inverting the output on every 50MHz clock cycle).  I am not aware of a way to directly wire an internal clock to a digital output pin in LV FPGA.  However, there are two options to generate a 50MHz clock at your output pin:

1. Run your SCTL at 100MHz, use the same logic described above (invert output on every clock cycle)

2. Get creative with the HDL node

Option 1 may be difficult as it requires a faster clock source.  Check your target documentation to see what your options are here.  I don't believe your target supports LV FPGA derived clocks, but you may be able to use another source.  Be aware that it is more difficult to meet timing when compiling for faster clock rates.

Option 2 requires you to write HDL code within the HDL node and configure the DIO in LV FPGA to correctly pass the signal.  Disclaimer - this method bends some of the underlying assumptions of LV FPGA execution flow, but it will get the job done.  Read on if you dare :).  Your HDL code could either directly assign the 50 MHz clock input to an output, for example:

DigitalOut <= Clock50;

Or you could instantiate a Xilinx ODDR component (see Xilinx Spartan 3E documentation).  The ODDR component has 2 inputs and will drive a new value to its output on every edge of a clock (rising and falling).  Therefore, you can wire one input to a static '1', and the other to a static '0' to get a copy of the clock on the output pin.

In either case you wire the output of your HDL node directly to a LV FPGA Digital Output in a SCTL.  You must set the # of synchronization registers on this Digital Output to zero.  This will prevent LV FPGA from inserting a Flip-Flop between the output of your HDL node and the Digital Output pin. 

Now you should have a copy of your 50MHz clock on your output pin.

Good luck!

-RB

[troy.perales]

I have tried option 2 exactly as you ahe described using the folling code:

entity Clock is
   generic(
      ClockFrequency : Integer := 50000000;
      InSingleCycle : boolean := true
   );
   port(
            clk : in std_logic;
            reset : in std_logic;
            enable_in : in std_logic;
            enable_out : out std_logic;
            enable_clr : in std_logic;
            clk_out : out std_logic_vector(0 downto 0)
   );
end Clock

architecture implementation of Clock is
begin
    clk_out(0) <= clk;
    enable_out <= enable_in;
end implementation;

I tied the clk_out signal directly to an Expansion Connector I/O Node within an SCTL and got no output. I've tried looking for the option to change the synchronization registers to 0, but can't find it. When I go to the properties of the Expansion Connector I/O Node, I find the following message:

FX2_IO1_J1_0 : No Node Specific Properties Available

[RyanB]

The synchronization register setting for a digital output is set via the properties menu for the IO listed in the LV Project (not via the IO in the LV diagram).  Therefore, you need to Right-Click on the IO you are using in the LV Project to change the arbitration settings and the # of synchronization registers. 

Even with the extra synchronization register you should still get something at your output.  Are you sure your output is enabled?

-RB

[troy.perales]

Found it and it worked!!!

Makes sense since the output was being updated by the same clock that i was trying to read. So the output was updating; however, it was updating when the clock was in the same position.

Thanks you so much for your help, Ryan!