NI9217 FIFO Full problem

[GRixon]

Hello all, I've run into a bit of a problem using DMA FIFO to pass data to my RT host and I'm hoping someone might be able to see where I'm going wrong.  I'm using a cRIO-9002/9102 chassis with NI 9217 RTD modules.  I've attached my FPGA VI for reference.  I've set up 2 target-host DMA FIFOs, one for grabbing my module calibration values and one for passing the actual RTD values.  The first is set (right now) for 15 elements (only need 8 at the moment), and the second for 7 (only need 4 at the moment).  FIFO 1 is running on DMA channel 0 and FIFO 2 is running on DMA channel 1.  As far as I can tell, I've set everything up correctly, but I have two problems.  First, everything seems to run just fine when I'm only passing 8 values to my 15 element FIFO, or 4 to my 7 element FIFO, but eventually I'm going to want to do a bit more dynamic data transfers and make use of the FIFO Full flag, which doesn't appear to work at the moment.  I've padded my first data array with 8 zeros, so I'm trying to pass 16 elements to a 15 element FIFO, and the FIFO Full never trips to True, and my VI hangs right there...any idea what I've done wrong here?  The second question is that in my host VI, when I read the 8 elements from the FIFO (normal operation, just 8 elements and no padded zeros) I use an unbundle to break out all the individual values.  The problem is that the unbundle is sizing itself to 9 elements instead of 8 and I'm not sure why...is this something to do with the 0 based indexing of the FIFO? I'd thought that the 'Number of Elements' on the FIFO Read block was the total number but maybe its the index to read up to?  Any help would be greatly appreciated.

Thanks,

-Greg

[Dustin_W]

Hi Greg-

When FIFO Write is called it tries to push an element into the FIFO up to the amount of time specified in the timeout input.  In your code, you have the timeout specified as '-1', which means try forever.  When your FIFO is full and not being emptied, the FIFO Write never returns because you told it to keep trying forever.  If you want a Boolean that your FIFO is full, use a timeout of 0 instead.  Just note that doing so will result in dropping a element of data if the FIFO is full.  As a side note, the buffer full Boolean is logically equivalent to a timeout Boolean, and in fact in LabVIEW FPGA 8.5, the buffer full Boolean's name has been changed to 'Timed Out?'.

Second question was about the unbundle creating 9 elements.  I am guessing you must be using the Array to Cluster.  Since Arrays can have a dynamic size, and clusters must have a fixed size, you have to specify the size of the cluster you want to create.  This is done by right clicking on the Array to Cluster and selecting If you right click on the Array to Cluster and selecting Cluster size.  This defaults to 9.  Incidentally, you probably want to be use an index array or decimate array rather than converting to a cluster.

I hope that answers your questions - Just a couple of other notes on sizing your FIFOs.  It typically isn't necessary to size your FIFO to the number of data points on your FPGA, I usually recommend leaving the default FPGA FIFO size (1024) unless you have a good reason to change it (e.g. running out of room on the FPGA)  Larger doesn't hurt, and in fact gives you a little more flexibility when you have multiple DMA channels trying to write at the same time.

-Dustin

[GRixon]

Dustin,

Thanks so much for your quick reply, that solved the problem.  I'm using version 8.2 so that little tidbit of information isn't in any of the help files, it just says it will flag full if you try to write an additional element once the FIFO is full.  Also thanks for the tip about the array manipulation, I'm new to LabVIEW and there are clearly many ways to get things to work, so I am still trying to learn the best ways to do these things.  The index array I could use in a loop to pull out all the individual values, which would take up less space in my VI diagram but it uses a loop.  If I use several decimate array blocks in sequence it would take up more space in the VI but avoids the loop...which is a more efficient way to do it?

Thanks again,

-Greg

[NoahR]

Hi Greg,

It's good to hear from you again!  As for your question about using the index array versus the decimate array, I would suggest using the index array in a loop.  Usually, the decimate array is used for when you are trying to get chunks, or more than one element, of an array out at a time.  And if I am understanding your problem correctly, there is no need to worry about using a loop to do this.  This is usually the way we do it here and recommend getting the single values out of an array.  I hope this helps and feel free to post back if you have any more questions.  Thanks!

[Dustin_W]

Hi Greg-

I'm glad the info helped.  As far as using index array and decimate array, there are cases where each makes sense.  If you only need a single sample of data such as when you are reading your Cal Data FIFO, the index array makes the most sense.  The index array lets you index out more than one point at a time, so you shouldn't need a loop.  Just grow it to pull out the data you need - in your case, it looks like you are writing 8 elements of Cal data (or 16 if you keep the padding with zeros at the end), so you could just grow your index array to look like the following

Note it is not necessary to have inputs on the left-hand side.  By default it starts at index 0 and continues in order (1, 2, 3, etc.).

If you are looking more for a buffer of data, decimate array can be very useful.  It takes the one large array and divides it back out to several small arrays.  So you could read 1000 points from your RTD Data FIFO (250 samples per channel) and decimate it out to 4 arrays, 1 for each channel.   Again, it is a growable structure so just make it match the number of channels you are pushing in on the FPGA side:

-Dustin

Message Edited by Dustin W on 11-15-2007 09:34 AM