One Question on the Online Tutorial "Developing High Speed Continuous Buffered Data Acquisition Applications with CompactRIO"

[Kjell-E]

In the following example\tutorial, I have one part which I can not make any sense out of:

http://zone.ni.com/devzone/conceptd.nsf/webmain/8E999A74E43AC76186256F5E0068CFAC?opendocument&node=dz00000_us

Look at "figure 1", that is, the figure off the Buffered DAQ (FPGA).vi

In the bottom left, there is a while loop "Empty FIFO".

Now, first of all, I dont understand the wire that runs out from this while loop and up to the "aquisition and buffering" loop, because it just ends there in empty space. Since it does not go anywhere, I guess it must be there to control the flow of the data and thus the rate it runs at?

Secondly, I do not understand its purpose at all. The "Communication to Host" is where the data in the FIFO is read and passed on to the RT host is it not? So why are there two different loops reading the FIFO?

I hope that someone can help me understand these two things!

Many thanks in advance!
Kjell

[Kjell-E]

I would realy appreciate some feedback here!

[EdDickens]

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Look at "figure 1", that is, the figure off the Buffered DAQ (FPGA).vi

In the bottom left, there is a while loop "Empty FIFO".

Now, first of all, I dont understand the wire that runs out from this while loop and up to the ""quisition and buffering" loop, because it just ends there in empty space. Since it does not go anywhere, I guess it must be there to control the flow of the data and thus the rate it runs at?

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You're correct, it just ensures that the "Empty FIFO" loop runs to completion before the "Acquisition and Buffering" loop can start. This way the FIFO will be empty and only contain newly acquired data.

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Secondly, I do not understand its purpose at all. The "Communication to Host" is where the data in the FIFO is read and passed on to the RT host is it not? So why are there two different loops reading the FIFO?

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The "Communication to Host" loop simply reads data from the FIFO and passes it to the host. The data is actually read from the analog inputs and written to the FIFO in the "Acquisition and Buffering" loop.

Usually you would set something like this up so that passing data to the host won't interfere with the actual acquisition process.

Ed

[GValdes]

Hi, Kjell,

In this example program, the purpose of the Empty FIFO loop and the wire that runs from it to the border of the Acquisition and Buffering loop is just to make sure that the FIFO is emtpy before the acquisition starts running. The "unconnected" wire is not really used to control the rate of the program, just its flow of execution: basically, when the FPGA program starts running, the Communication to Host loop starts running and the acquisition loop will not start running unless the FIFOO is emptied first. That way, you can guarantee that the FIFO hasn't anything stored in it before you start writing to it.

I hope this helps!

GValdes