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PSK demodulation

I want to demodulate a pulsed PSK signal,

the signal is build up like this:

Frequency: 406,028 MHz -> downconverted to 6,028 Mhz
Total pulse time: 520 ms
pure carrier: 160 ms 
Modulated part: 360 mS (offcourse)

Modulation: BPSK at a baud rate of 400 SPS, the phase begins at 0 and than switches between 1.1 and -1.1 Rad.

What I have done so far is downconvert the signal to approximatly 6 MHz and than save a selection of the pulses to one file with the HWS storage VI's (saving with it a lot of info (gain and offset, sampling rate) (5 times oversampling)).

Than I made a routine that can read one pulse and chunk it up to stream it to an other program part where I want to process it...

Now is My question, does anybody allready written a good demod program for BPSK, otherwise where can I find a good description for this. I do have the modulation toolkit...

Best regards
Joost van Heijenoort

Engineer at Ursaminor space and navigation.

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Message 1 of 8
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Dear Joost,

The Modulation ToolKit includes two example that shows how to do PSK Demodulation. These example includes BPSK.

You can find the Example in the Example Finder under: Toolkits and Modules -> Modulation -> Digitizer -> MT niScope PSK Demod.vi or MT niScope PSK demod (5122).vi

Hope this helps

Regards,

Karsten

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Is There somewhere a good discription on how the Tools in the modulation kit work....

This because i have trouble making a program that can demodulate the upper signal. Frankly at this moment i am not sure what i am doing....

regards

Joost
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Message 3 of 8
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Hi Joost,
 
Please check the help-file:
 
 'This because i have trouble making a program that can demodulate the upper signal'.
What would you like to know?
 
Regards,
 
Bas van Dijke
AE, Netherlands
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Message 4 of 8
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Hee Bas,

Do you have an direct email adres?

gr
Joost
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Message 5 of 8
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Joost,

My emailadress is: bas.van.dijke@ni.com

Regards,

Bas

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hello,
i am working on LV PCI 5640 R, i am not able to do  Modualtion of PSK(BPSK etc..)signal in the FPGA vi. please help me how to create the FPGA part.

thanks.
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Message 7 of 8
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Hi IF-RIO,
 
Please post your question on the forum linked below.
 
Regards,

Bas van Dijke
AE, Netherlands
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