Pass value to FPGA I/O node in FPGA.vi from Host.vi

[clint100]

How do you pass a different value to the FPGA.vi I/O node from the Host.vi??  In the FPGA I made the I/O node a "control" but when I try to use Read Write control in my host none of the I/O show up in the drop down selection.  All my booleansare there.   See screen capture.

Thanks..

[Ben]

You have to recompile the FPGA code and then relink to the new version for the control to show up. The "wire" has the infor on the control and if you are using an wire that did not know about the new control...

Ben

[clint100]

Ben

I recompiled my FPGA vi and the FPGA I/O still doesn't show up in my Host.vi.  I deleted the "Open FPGA VI reference", recreated it and then relinked it to my FPGA.vi.  Maybe I didn't explain it well enough??  I have a Host vi that "calls" a FPGA.vi.  My connector I/O changes from one test to another but my vi logic is the same.  I just want to chg connector I/O from one test to the other ( in my host.vi) w/o recompiling the FPGA.vi each time.  My booleans and integers show up in the Read/Write Control but not the fpga I/O connector names.  IE DIO 0, DIO1, etc.

[nathand]

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@clint100 wrote:

I recompiled my FPGA vi and the FPGA I/O still doesn't show up in my Host.vi.  I deleted the "Open FPGA VI reference", recreated it and then relinked it to my FPGA.vi.  Maybe I didn't explain it well enough??  I have a Host vi that "calls" a FPGA.vi.  My connector I/O changes from one test to another but my vi logic is the same.  I just want to chg connector I/O from one test to the other ( in my host.vi) w/o recompiling the FPGA.vi each time.  My booleans and integers show up in the Read/Write Control but not the fpga I/O connector names.  IE DIO 0, DIO1, etc.

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You cannot read and write directly to the IO pins from the host VI; everything goes through the FPGA.  You can write some simple FPGA code that passes values directly from a control to an IO pin.  Alternatively, if you use the Scan Engine I think this has already been done for you, although I have not personally used the Scan Engine features so I can't tell you exactly how it works.  My understanding is that it does provide direct access to the FPGA IO without needing to write any FPGA code, and there is a "hybrid" mode in which you can write some of your own FPGA code while also using the automatic IO access.

[clint100]

So I have to hardcode in the connector names in my fpga.vi??

[nathand · Accepted solution]

That's exactly right.  Remember, when you compile an FPGA VI you are essentially creating the hardware and assigning logic directly to IO points.  You can use a case structure to route data to the appropriate IO channels for the test you're running if you have a set of specific channel assignments for each test.

[nathand]

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@Ben wrote:

You have to recompile the FPGA code and then relink to the new version for the control to show up. The "wire" has the infor on the control and if you are using an wire that did not know about the new control...

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By the way, if you're using a reference to an FPGA VI (and not a bitfile), there's no need to recompile to pick up changes to the controls on the front panel of the FPGA VI.  However, IO node references do not propagate to the host VI.  The reason for FPGA IO node controls is for subVIs within an FPGA design, not for host-to-FPGA communication.

[GregFreeman]

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@nathand wrote:

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@Ben wrote:

You have to recompile the FPGA code and then relink to the new version for the control to show up. The "wire" has the infor on the control and if you are using an wire that did not know about the new control...

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By the way, if you're using a reference to an FPGA VI (and not a bitfile), there's no need to recompile to pick up changes to the controls on the front panel of the FPGA VI.  However, IO node references do not propagate to the host VI.  The reason for FPGA IO node controls is for subVIs within an FPGA design, not for host-to-FPGA communication.

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Unfortunately, this really is a bit misleading. When I was first learning FPGA, I got caught up in this when I tried to use a config file to set the IO nodes up like you would for DAQmx. I understand why it isn't really possible, I just wish there was some way it would notify the programmer of this. I even took the FPGA class from NI and I don't think they ever mentioned this was not possible.

I do like the idea of routing the signals using a case structure though, that's a good idea. The only issue is if you want to have all channels available without a recomile, you have to acquire from them all even when unused, just in case the user decides to use them down the road.

[clint100]

If I have a Host.vi and a FPGA.vi and the only "values" changing are my connections ( have PXI7853R), can I have one Host vi and multiple fpag.vis in my project???  The multiple fpga vis would each have the connectors hard coded in them.  If yes, how do I know which bitfile goes w which fpga.vi.  Using the bitfile because I'm using the host vi in Teststand and from what I understand from discussion/knowledgebase you use the bitfile in teststand.  When you recompile the fpga vi does it overwrite the current bitfile ??

Thanks.

[nathand]

Yes, you can have multiple FPGA VIs, and load whichever one you need.  You would need to place several Open FPGA VI References in the host VI, probably in a case structure so that only the correct one executes and loads the corresponding bitfile onto the FPGA.  Each FPGA VI is associated with a specific bitfile name (at least prior to LV2011, which introduced some new options), so recompiling an FPGA VI will overwrite the existing bitfile for that VI but will have no effect on other compiled FPGA VIs and their bitfiles.  Also, you can rename the bitfile, make changes, recompile and then have two different bitfiles.  You can change the Open FPGA VI Reference to refer to a bitfile instead of a VI, and then pick the appropriate bitfile.

I know nothing about Teststand nor how it interfaces with an NI FPGA board.

How many possible IO combinations do you have?  It might be easier to have a case structure in the FPGA code that selects the appropriate channels.  If you go this route, it is probably more efficient to put the FPGA IO on the block diagram only once - outside of the case structure - and handle only the routing inside the case structure.  If you need more flexibility than that, you could pass an array or cluster to the FPGA that contains a mapping of data to IO channels.