How often are you switching between projects? If you're doing it frequently, or the time involved in switching is a problem, then loading a new bitfile may not be the way to go.
For only three channels it would be easy to set up a map. If FPGA space allows, I'd create a large boolean array of all false values, use the map to insert the logic values into the correct locations, and write out that entire large array to the real IO channels (fewer wires if you do this as ports rather than lines, and probably the same amount of FPGA logic).
