Problems using a High Thoughput Add and Multplier in to a Single Cycle Timed Loop

[flote]

Hi friends I’m designing a FIR filter in the next FPGA System:

And before to implement all the stages of a FIR filter I have tried to implement a simple Multiplying using the Math Throughput Match Module:

 

And when I compile the program I get the next error:

If I use another clk source the problem this problem is solved, but I can not do it, because I need to implement the FIR filter in the same Timed Loop of the ADC acquisition. And the ADC only can works with the IO Module Clock 0.

Anyone has any idea about this??

Thank to everybody and have a nice day!

[craigc]

Not sure,

The only bit of insight I get from that message is that the clock you are using is a derived clock and therefore it is not running constantly which gives you the error.  Why do you need the FIR and the ADC in the same loop?  Can you not put the FIR in a faster loop and just latch or FIFO the ADC data across?  I know this is crossing a clock domain (I thinik) but may be the solution.

Craig

[flote]

Hi Friend! Thank you very much for your quick answer....

I need the FIR in the same LOOP of the ADC because I need to do a Online Acquisition without any stop. If a put the FIR in other LOOP I have to stop de acquisition, FILTER the sampled and after going on with the acquistion again. This point I have already checked oin the next way and it does not work properly:

1) Timed Loop single Cycle (Acquisition LOOP): I acquiere samples from the ADC at 125Mhz (IO module CLock 0) and thouse samples are stored in 2 FIFO's. I start to store the samples in the  FIFO 1 and when it's full I continue storing the samples in the FIFO 2 and after I store in the first one again and so on.

2) While Loop (Transfer to Host LOOP):Read the FIFO's in this way: While I'm acquiring samples with FIFO 1, I read the data from the FIFO 2 and it's sent to the HOST. And While I'm acquiring samples with FIFO 2, I read the data from the FIFO 1 and it's trasfered to the HOSTand so on.

Here is my current problem: The FIFO’s are full (Acquiere Loop) before I read all the Data from them in the While Loop. It’s logical because the acquiere loop run at 125 Mhz. But what about the While Loop? I don’t know which CLK use it. But It’s slower than 125 Mhz for sure. This is a question that I need an aswer..…..So I can’t do Real Time Filtering acquisition because I have to wait at the FIFO’s are totally read…Do you have any idea how can do it?? I don’t understand very well when you said “latch or FIFO the ADC data across”. What do you mean exactly?

Thank you for yout help anyway.

[flote]

nobody know anyhitng aobut this? Please I am not able to run this programm...

Thank you