RT HOST VI and FPGA vi communication

[suni]

Hi,

In my application i have RT host vi and FPGA VI. i am using DMA FIFO transfer data and display in RT HOST VI. Also I am using FPGA read/write nodes in RT host vi to write to controls in FPGA VI  to output data using digital I/O modules. When i run the rt host vi it looses connection. only way to rerun the program is to physicaly hit reset button in rt target. Is there a way to fix this?I using LABVIEW 8.6. Thanks.

[AdnanZ]

What loses connection? Are you talking about the RT front panel that you are viewing on Windows or the RT VI itself loosing connection to the FPGA? Post an isolated version of your project and a snapshot of the error so it becomes easier for us to visualize your issue. At this point, I suspect it's a problem of not assigning the right timing and priorities to the loops (in RT) and not creating the right architecture to run your project.

[suni]

Hi 

Thanks for the reply.

RT front panel that is in windows pc looses connection. I have only one loop in RT vi now. I reduced the loop rate of my SCTL in my RT vi then it started to work. But I need faster loop rate because I want to be able to write to digital I/O module and have data avilable deterministicaly. Before I had 2 RT loops referencing to 1 FPGA VI. One for writing data to boolean control in fpga vi and other one for read data from DMA FIFO and calculate and display PSD  and RMS values. I am sampling 25ks/s in FPGA VI. and reading at 1000 samples at time in RT vi.This method didn't work really well (very slow). Could you tell me best way to do this? Thanks.

[AdnanZ]

You have already got the answer to your question. You shouldn't be using the RT front panel to communicate with the RT block diagram code since you have unconsciously created the user interface thread that is starved when your SCTL runs at a very fast speed (it has higher priority as well). All you need to do is to create another loop that programmatically communicates with your host, probably using shared variables or native tcp/ip nodes. And, another loop in your host that reads the data values and does the user interface.

[nathand]

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suni wrote:

Hi 

Thanks for the reply.

RT front panel that is in windows pc looses connection. I have only one loop in RT vi now. I reduced the loop rate of my SCTL in my RT vi then it started to work. But I need faster loop rate because I want to be able to write to digital I/O module and have data avilable deterministicaly. Before I had 2 RT loops referencing to 1 FPGA VI. One for writing data to boolean control in fpga vi and other one for read data from DMA FIFO and calculate and display PSD  and RMS values. I am sampling 25ks/s in FPGA VI. and reading at 1000 samples at time in RT vi.This method didn't work really well (very slow). Could you tell me best way to do this? Thanks.

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Can you clarify wat you mean by "SCTL in my RT"?  SCTL is a single-cycle timed loop which exists only on the FPGA, not in the RT code.  You do need to slow down your RT code in order to allow the front panel communication thread enough processor time.  Can you use larger FIFOs, and process the data in larger chunks?  This might allow you to run your RT loop at a slower speed but still maintain the same data acquisition rate.  You could also use the same size DMA FIFO but instead of immediately processing that data, put it into a queue or RT FIFO, then let another loop in the RT code handle your analysis at a slower rate by reading from that queue or FIFO.  When you say "really slow" how slow is that?  Which part needs to be faster?  How frequently do you need to calculate PSD and RMS values?  If you're just looking at it on the screen there's no need to update any faster than about 5x/second, whereas right now it sounds like you're updating 25x/second.

[suni]

Thanks for the reply.

I wanted to say timed loop in my RT vi. I thought SCTL and timed loop are the same. That was mistake. sorry.

I have two DMA FIFOS for 2 signals set at 8192 elements in FPGA. In RT vi I am processing them (FIFO read function) 1000 elements at a time. I can try to use larger FIFO. How slow should i run my RT loop?  Do two DMA FIFO make proccesing time in RT loop slow?

 When i had 2 loops one for  analysing and update controls it took significant delay to update the graphs when i changed the signals. I want to read PSD and RMS every 20ms. I am not just looking at those graphs, i am using those RMS to update controls in the FPGA VI.

Thanks.

[nathand]

Would it be possible for you to post your code?  There's no way to say what your loop time should be in order to leave time for the user interface to update; it depends on what is happening in your loop.  You could be running 100ms loops but if the processor is never idle during that 100ms then you'll probably lose your connection to the RT system.  I wonder if there's some inefficiency in your analysis functions.  If you run your loops half as fast and read twice as many elements out of the FIFO each time, does it solve your problem?  Have you looked at the Distributed System Manager (this may further burden your processor) or the execution trace toolkit (if you have it) to see how much processor time you're using?  What mechanism are you using to limit the RT loop cycle time?

[Jon_S.]

suni,

I think Adnan Z and nathand hit the nail on the head.  You need to put everything that is time-critical (data acquisition and processing) in one timed loop with a higher priority.  The loop that controls the user interface needs to have a separate loop that has a lower priority.  This will force the controller to execute the high priority loop at the correct speed, then when the processor has time, it will execute the low priority loops.  There is a basic framework for this that is shipped with LabVIEW.  Select File»New and then browse to Project»Project from Wizard»Real-Time Project. Pick a name and click Next.  Then choose the box to include a user interface.

I have included a screenshot of the block diagram of this template.

[suni]

Hi

Here is my RT code and FPGA vi. For your question "What mechanism are you using to limit the RT loop cycle time? " I am not sure how to do this. I am running rt loop at 20ms now and it is functioning faster than before. But I would like to see ways improve my code.Thanks for your help.

[Jon_S.]

suni,

Your timed loop will run at the specified dt unless it cannot complete all of its code in the given time.  If you are looking at optimizing your FPGA code here is a good DeveloperZone Tutorial.