Read/Write Control Function in FPGA target?

[maherhome]

Hi folks,

I'm learning alot from the FPGA sample project, including how you can easily retrieve and set controls and indicators in a running FPGA using the Read/Write Control Function in an RT target.

However, I can't seem to find a way to do something similar in an FPGA target.  I've been down this road before - i.e., trying to move data in/out of a looping FPGA (sub) VI to an FPGA (parent) VI - resulting in my using Memory Items to achieve what I needed.  

So I was excited to see the FPGA pallete allowed me to drop Read/Write Control Functions onto an FPGA target vi.  But alas there where tons of errors (wires not compatible for target, etc.) and I now assume it's not possible.

So just to be sure I'm not missing something, is there something like the Read/Write Control Functions to use in one FPGA to read/write to another (looping) FPGA?

Also, why would I be able to put the Read/Write Control Functions on an FPGA vi if they're not supported?  (sorry for the n00b question)

Thanks,

Steve

[nathand]

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maherhome wrote: 

So just to be sure I'm not missing something, is there something like the Read/Write Control Functions to use in one FPGA to read/write to another (looping) FPGA?

Also, why would I be able to put the Read/Write Control Functions on an FPGA vi if they're not supported?  (sorry for the n00b question)

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Memory items or FIFOs are appropriate for moving data between FPGA loops.

At least in LabVIEW 2012 on my machine, I don't see Read/Write Control in the palette when I right-click on on the block diagram of a VI in an FPGA target. It's possible to drop a Read/Write Control node there by dragging it from some other VI and it will appear in the FPGA block diagram, but that doesn't mean it will work. You can do the same with a .NET property node (as an example) which of course can't run on an FPGA. Are you seeing it in your palette when you work with an FPGA VI?

[maherhome]

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@nathand wrote:

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Memory items or FIFOs are appropriate for moving data between FPGA loops.

At least in LabVIEW 2012 on my machine, I don't see Read/Write Control in the palette when I right-click on on the block diagram of a VI in an FPGA target. It's possible to drop a Read/Write Control node there by dragging it from some other VI and it will appear in the FPGA block diagram, but that doesn't mean it will work. You can do the same with a .NET property node (as an example) which of course can't run on an FPGA. Are you seeing it in your palette when you work with an FPGA VI?

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You are correct that I do not have that node in my palette.  However, I also don't seem to have an Occurrence Refnum in the palette either in FPGA mode (see below), but I needed it to synchronize multiple FPGA loops and was able to add it using the search textfield in the VI editor (and if compiles and runs).  So 6 months in to Labview and I'm fuzzy about how the palette is constrained.

Concerning read/write FPGA controls/indicators, I'm surprised that the infrastructure developed to allow read/write between RT and FPGA hasn't been leveraged to allow read/write between FPGA and FPGA.  Memory Items work, but they're less convenient.

Steve

[nathand · Accepted solution]

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@maherhome wrote:

You are correct that I do not have that node in my palette.  However, I also don't seem to have an Occurrence Refnum in the palette either in FPGA mode (see below), but I needed it to synchronize multiple FPGA loops and was able to add it using the search textfield in the VI editor (and if compiles and runs).  So 6 months in to Labview and I'm fuzzy about how the palette is constrained

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I'm not sure what you're trying to demonstrate here. There's no refnum control in the search box in your image . Occurrences are available in FPGA, and to get a refnum control for one you just right-click on an occurrence function and create a control. If you can create a valid wire of a certain datatype, then you can create a control or indicator for it, regardless of whether that control or indicator type appears in the palettes. However, the functions you can use in the block diagram are limited by what's available in the palettes.

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@maherhome wrote:

Concerning read/write FPGA controls/indicators, I'm surprised that the infrastructure developed to allow read/write between RT and FPGA hasn't been leveraged to allow read/write between FPGA and FPGA.  Memory Items work, but they're less convenient.

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You might have noticed that you can't compile individual pieces of an FPGA VI and then combine them later; that's because when you compile an FPGA VI, all its subVIs are essentially merged to create a single block diagram (with added logic if a non-reentrant subVI is used in multiple locations, which is why that's not recommended on FPGA). The subVIs no longer exist in the compiled FPGA; reading and writing a control on them would be meaningless. If you want comparable behavior, use global variables - but understand that global variables store their values in FPGA logic resources. Using memory items (or FIFOs, which can also store in memory) leaves more FPGA logic fabric available by storing data in resources specifically designed for that purpose.

[maherhome]

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@nathand wrote:

I'm not sure what you're trying to demonstrate here. 

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I'm demonstrating I'm still on a learning curve.

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You might have noticed that you can't compile individual pieces of an FPGA VI and then combine them later; that's because when you compile an FPGA VI, all its subVIs are essentially merged to create a single block diagram (with added logic if a non-reentrant subVI is used in multiple locations, which is why that's not recommended on FPGA). The subVIs no longer exist in the compiled FPGA; reading and writing a control on them would be meaningless. If you want comparable behavior, use global variables - but understand that global variables store their values in FPGA logic resources. Using memory items (or FIFOs, which can also store in memory) leaves more FPGA logic fabric available by storing data in resources specifically designed for that purpose.

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I understand what you're saying, but I wouldn't think the merging process itself precludes hooking up in's and out's of FPGA subVI's.  The Read/Write Control Function describes how an FPGA-specific register map is created for the data flow to/from RT.  Seems like the same mechanism could be used to wire up to/from FPGA subVIs during the merge process.  But I'm probably missing something.  Thanks for your help.

Steve