Replace quotient and Remainder with Scale by power 2

[S.T.E]

I want to replace quotient and Remainder function with Scale by power 2 to reduce resource usage on FPGA.

Here is my problem, I want to achive the same result, but no sure if the code will allow me to input the value I need, i also am not sure what that value should be?

[Florian.Ludwig]

Hi,

the example works because 1/4 = 2^(-2).

Your n will always have to satisfy the equation n = -lg(d),

where lg is the logarithm to the base of 2 and d is the divisor you want to replace.

This only works if d is a power of 2 of course

Best regards

Florian

[crossrulz]

What are you trying to divide by?

[S.T.E]

I begin with a numeric of 12345678

I then want to lose the first number (1) to leave 2345678 so divide by 10000000

From this I will carry out the same function but divide by 1000000 to leave the result of: 345678

so on and so forth unitl I finally divide by 10 to just leave the 8

The quotient and remainder allowed me to do this, but on FPGA has high resource usage.  So i was hoping to achieve the same but by scaling by power 2?

[Florian.Ludwig]

Oh, I overlooked that you care about the remainder, not the quotient.

Is it only the least significant digit you care for?

[S.T.E]

I will need the result from every operation at each stage:

So I can have a total of 8 results to do with as I please.

hope this helps my definition.

[Florian.Ludwig]

I think I got you now.

The problem is I don't know what's expensive in RT.

Scale py power 2 won't help you here because your divisors are never a power of two and it only gives you the quotient anyway, not the divisor.

I'm not a computer science graduate, but I guess fast here means binary friendly operations - and those are hard to use for your decimal problem.

How expensive (if it can be done at all in RT) is it to convert your number to a string and then convert the easily exractable digits back?

[S.T.E]

I dont think strings are available in FPGA.  I appreciate you input though,  it may be that I try to streamline else where. mmm interesting one...

[crossrulz]

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@Florian.Ludwig wrote:

The problem is I don't know what's expensive in RT.

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The OP is asking about FPGA, not RT.

RT is fine with the Quotient & Remainder.  It'll take a few clock cycles of your processor, but that is nothing in the rates for an RT system.

An FPGA is a different beast since you need to look at how much of your FPGA hardware you are using up.  Bit shifting (which is what the power of 2 actually does) is dirt cheap in an FPGA.  But divisions are really expensive to do.  But since you are dealing with powers of 10, you are kind of stuck.  Hardware (FPGA in this case) works best when dealing with binary (ie powers of 2).

So what device is this one?  How fast do you need these outputs?  It might make sense to pass some of the data up to the RT system and then the RT can pass the results back down to the FPGA for actual output.

[Florian.Ludwig]

Thanks for clearing that up. 

I'm so distant from that field that FPGA and RT were in the same pot for me.

Learned someting.