Synchronizing DMA FIFO Buffers

[SierraNevadaAaron]

I just tried the 'enable writing to the buffers simultaneously after they've been configured and started' approach and I'm still seeing buffer offset issues.

I would like to try the interlaced approach but I'm using an FPGA timed loop so will it be possible to write to the FIFO multiple times?

[nathand]

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SierraNevadaAaron wrote:

I was a bit worried about doing something like interlacing the channels due to performance issues on the host side. Is this common practice and I shouldn't be worried about performance on the host? In any case, great suggestions guys, thank you.

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I would say this is common practice, based on forum posts and personal experience.

A good rule about performance is not to worry about it until you can demonstrate a bottleneck. Of course you should strive to write good code, but don't attempt more optimization than that unless actually necessary. The LabVIEW compiler gets better each version and can often optimize for you. For example, LabVIEW can efficiently de-interlace if the decimation factor is known at edit-time: one of the "under-the-hood" optimizations is the use of "sub-arrays" where instead of copying all the data into a new array, LabVIEW creates a reference to some subset of data within the original array. That new reference also includes a "stride" - the distance between elements of the new sub-array within the original array - which makes decimation simple and fast.

[nathand]

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@SierraNevadaAaron wrote:

I just tried the 'enable writing to the buffers simultaneously after they've been configured and started' approach and I'm still seeing buffer offset issues.

I would like to try the interlaced approach but I'm using an FPGA timed loop so will it be possible to write to the FIFO multiple times?

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Any chance you can share your code? This sounds like you're doing something wrong. The host should start both DMA channels, then set a flag to tell the FPGA that it's safe to put data into the DMA buffers. From there, if you always put data into both FIFOs at the same time, and on the host you always read the same number of elements from each one, there's no reason they would get out of sync.

Do you write data to the DMA FIFO on every iteration of the timed loop? You can't write to the FIFO multiple times in a single-cycle timed loop.

[SierraNevadaAaron]

For my company's sake I cannot post all my code but here are some screenshots of the buffers.

Notice the DMA to Host boolean which enables the FIFO writes.

[nathand]

How large are the DMA FIFO buffers? I assume they're both configured for the same size. Do you also configure the host-side buffers? Why are you trying to read 65536 elements? It might be better to read as many elements as are available in both buffers (ie, the minimum of the number of elements in each) at the same time instead.

How do you know you're getting an offset between the two DMA buffers? What is the pattern of data? What if you simplify your code for testing, and write the loop iteration to the DMA FIFOs instead of the data you're pulling off the ADC FIFO, so you can check if the problem is in the DMA FIFOs or somewhere else in your code (for example, wherever you're loading data into the ADC FIFO)?

Do you ever check for timeouts, either when pulling data off the ADC FIFO, or when writing it to the DMA FIFO? I see you're doing something with the timeout from the ADC FIFO but can't tell what, and you could potentially lose a piece of data if one ADC FIFO times out when the other does not.

[SierraNevadaAaron]

The buffers are the same length at 131072 samples.

I am reading 64k in order to process an FFT with the data.

To determine an offset I modified the FPGA code to load the FIFO buffers with pattern data instead of the true channel data, thus omitting any other contributer to the buffers. The pattern data is just an incrementing number; the same number loaded into each channel. Then, on the host side, I subtract each channel from every other channel. Ideally, since the numbers in each channel are identical, the results should be zero. For the channels that are in the same 64-bit FIFO buffer (2 channels x 32bits) the result is zero. For channels spanning both buffers it is non-deterministic and varies anywhere from 1000-2000 samples each time I start the program.

I do in fact have an indicator if the timed loop accessing the FIFO buffers does overrun, but nothing looking at timeouts. From what I can see, I can only configure the timeout of the .Read operation, I do not see a "timeout occured" flag.

For the purposes of fixing this sample offset I am going to gut the majority of my program code and focus on experiments involving some of your aforementioned ideas to assure channel synchronization.