Hi Gary,
Thanks for the reply. You are right that triggering clock signal also triggers the read.vi but problem is that I am looking for specific 12 bits of sensor output(in the rising edge of 16 clock cycles ). If there is an error of missing one clock, error is cumulative since I am reading with referenced to the only rising edge clock and first falling edge of chip select. If I could achieve to trigger my read.vi at each falling edge of chip select and read 12 bits at the rising edge of clock, I have only one time error since I am referencing each 12 bit samples separately to chip select also. I hope I can explain.
BTW, do you have any suggestions to read or combine 12 bits together(indexing between 4th and 16th clock cysles) in an efficient way (I am reading right now bit by bit with 1-Channel N sample Read.vi). If I read 16 samples per channel each time, I can easily achieve this. However, I need to work in high frequency(around MHz) so reading only 16 samples per loop results in buffer overflow(classic -200279 error)) . I have searched and found Producer/Consumer pattern. Do you have any other suggestions? I need to read in modwise such as my first data comes at 4th,20th,36th clock cycles(assuming no error), which may help.
Regards,
Ouz
