Using PXI clock in 5781

[sharath.halneer]

Hi,

I am trying to use the reference clock for 5781 adapter module. How can I use this. For example I would like to use the PXI clock of PXIe 1075.

Looking forward for an early reply.

Thanks in advance

[Rob_Ward]

sharath.halneer,

Do you mean you are using DAQmx - in which case this would be the DAQmx Timing.vi.  This means you would use hardware timing rather than the software timing of something like a wait (ms).vi timer inside a while loop or something similar.

But if you are using the Real Time or FGPA modules, then the functionality to mention would come from using a timed loop in Functions Palette -> Programming -> Structures -> Timed Loops.  It is essentially a while loop where you can specify the clock source, period & priority with greater accuracy, precision & reliability (keyword; determinism) than the windows 1kHz clock.

Hope this helps,

Regards,

[sharath.halneer]

Hey,

I am using a FPGA module. I have a 5781 adapter module and am checking for the latency of peer to peer data exchange between 7962 and high speed digitiser PXIe 5122. Hence, I need both the ADC's to run at the same clock speed.

So i was hoping to find a way to use the same reference clock for both the cards.

[sharath.halneer]

To add on, I want to phase synchronise both the adc's of 5781 and 5122. So that, both the sdc's will be PLL locked to a reference clock and i get same phse in both adc clocks. I can do this externally but 5122 CLK IN and CLK OUT are 10 MHz REF CLK and 5781 CLK IN and CLK OUT are 100 MHz sample clk so this cannot be connected externally.

So, I feel that only PXI 10 MHz clk can be synchronised here between the modules or I have understood it indifferently.

Any help really appreciated.

[florian.blaser]

Hi Sharath,

I'm currently facing the same problem with the same hardware. Did you by any chance solve it ?

I got the 5122 to sync to the PXI 10 MHz clock. Looking for a way to do the same for the NI 5781.

Thanks in advance for your reply.

Kind regards,

Florian

[David-A]

The 5781 is by default synched to the PXI Clk 10. If you right click the FAM and go to properties and then select the Details category you should see the IOModSynchClock is set to use the PXI_CLK10 as a reference. If you wanted to use a timing and synch module to sample at some arbitrary rate, this is where you would tell it to route the DStarA line to the ADC as a sample clock.

If you check page 8 of the 5781 user manual you'll see that the IOModSynchClk is routed to the clocking circuitry that in turn provides the ADC with a sample clock. By default, the AD9511 Clock Distribution chip is setup to use the PXI_CLK10 as its reference clock.