While Loop inside a Case Structure executes only Once in FPGA Target

[Ohitstarik]

I have a program made by a previous intern that i'm trying to clean up and get it to work properly. This program is just supposed to take data from an RPM sensor and display it on the screen, and write it to a TPMS log. 

The problem is from how it's running currently, the main "while" loop in the main program (host_PC_Energy_drone) only runs once (from the looks of it) and then stops updating data. So the data displayed on the screen only displays once and ends. What could be the cause of this? The stop case for the while loop is if the stop button is clicked, which it isnt. I'm at a loss here. 

[crossrulz]

Your FPGA loop can also end if there is a timeout on the FIFO.  That would point to something on the RT side being slow.  My first concern is your logging of data inside of your acquisition loop on the RT.  You should probably use a Producer/Consumer setup to put the logging into a separate loop so that the read loop can concentrate on doing just that and keep up with the FPGA.

[Ohitstarik]

It was that I didnt have a timeout value for the initial setup. must have erased it on accident and not realized.

The thing is we're getting data now, but super noisy. even though I ended up removing a ton of program code and cleaned it up it's still noisy. When we reduce the array and only try to log the RPM counter, thats when all the noise goes away and you get a decent looking graph.

Is this also because we're trying to log and acquire data in the same loop? So the program is struggling to keep up because it's trying to finish writing data to TDMS and go back to acquiring data?