LabVIEW
cRIO RT XNET code optimization
Our scenario is to use the cRIO-9035 as a datalogger to primarily measure analog and CANbus signals.
- Labview 2023 Q3
- 3 of NI-9853 2-port CAN cards. Each CANbus runs at 500 kbit/s and has ~30-50 signals as fast as 5ms.
- The FPGA for each acquires a 6 U32 array, checks ID and timestamp is diff and sends to the FIFO.
- 1 of NI-9205 Analog Input. Goal is to acquire at least 4 at 2kHz and 5 to 10 at 5 ms.
Currently the loop does work (as shown I’m testing with two 5ms msgs for ~9% bus loading), but the FIFO fills up and the FGV gets laggy presumably because it can’t convert the U32’s and store in FGV fast enough. I’m not entirely sure how to confirm that is the case and make it any better.
Please advise on any suggestions.
Hi Kinetics,
@KineticsTestEng1 wrote:
the FIFO fills up and the FGV gets laggy presumably because it can’t convert the U32’s and store in FGV fast enough. I’m not entirely sure how to confirm that is the case and make it any better.
Please advise on any suggestions.
First suggestion:
Clean code is easier to debug (and has less places for bugs to hide).
Don't you think the VI is way too large when looking at the navigation window in the lower right?
Other suggestions:
- After breaking down that large VI into several smaller ones you should have one VI handling the CAN0Read FIFO: you could implement a producer-consumer scheme here to have one loop doing just the basic FIFO read and another loop(s) to do the frame conversion/message+signal handling…
- Upon cleaning up you might remove coercion dots like those in the CAN-Write loop…
- When you need more detailed suggestions you should provide your code, not just a (truncated) image of code.
We cannot edit/debug/run images in LabVIEW…
