05-12-2008 05:51 PM
05-12-2008 07:16 PM
05-14-2008 03:57 PM
Hi Doug,
Are you using DMA FIFOs? If so, are they configured as Target to Host or Host to Target? If you change the timeout to -1 (never timeout) is the data read correctly?
05-15-2008 03:14 PM
Hi Jennifer,
I'm configured target to host. I tried -1 in both the read and write without success. I'm just trying to run the example program in chapter 8 of the cRIO Fundamentals course manual. The target is the same as the one on Figure 8-36 DMA FPGA with FIFO VI Block Diagram and the host is as shown in Figure 8-38. I'm getting the first read at the host, then nothing after that. The target is giving me a 65538 error.
Something is blocking me from enclosing attachments; that's why I haven't forwarded the VIs.
Thanks for the help,
Doug
05-21-2008 03:43 AM