extracting a portion of a signal on FPGA

[chlh]

Hi, 

I’m implementing logic on an FPGA to apply a window to an incoming signal during data collection, so that only the portion of the signal within this window is extracted. For example, I want to capture only the segment of the signal that lies between the Start and End cursors shown in Figure 1. My approach is to use a logic that checks whether the current data index falls within the range defined by the Start and End indices. However, I'm encountering timing violations during compilation. 

I am working with FlexRIO PXIe-5775 with an FPGA chip KU060. I’m developing my program based on the “Getting Started FlexRIO Integrated IO” LabVIEW example for the PXIe-5775. My current implementation is shown in the attached code. The section highlighted in Figure 2 was added to the 200 MHz Single-Cycle Timed Loop (SCTL) used for data acquisition. This portion transfers the acquired data—along with the outputs from the "Send Data" and "stream.samples transferred 0" signals in the Stream Control VI—to another SCTL operating at a lower clock rate of 160 MHz, as shown in Figure 3.

I implemented the range-checking logic in the slower clock loop to determine whether data should be sent to the DMA FIFO to the host. This logic functions similarly to the “In Range?” operation on the “In Range and Coerce” node. However, the compilation results shown below indicate a timing violation in the loop illustrated in Figure 2. I’ve experimented with many alternative designs, some with different structures, but this current version has the smallest timing violation so far. 

Can you help me with the code to avoid the timing violation? or is there a simpler way to implement the process of extracting a segment of a signal segment and transferring it to another loop for further processing? 

Thank you so much in advance!

[Terry_ALE · Accepted solution]

How big are your FIFOs that go from the 200 to the 160 MHz loop?  Making them smaller may help pass compiles.

Are you starting captures based on the analog trigger?

[chlh]

Thank you.

The FIFO is 16383 elements. The capturing is based on a digital trigger.

I just tried again with smaller size FIFO and it works. Now I wonder how it works... Can you refer me to the material that talks about how the FIFO size may affect run time? I do not remember this is explicitly said in the guides from the NI (maybe I did not read much enough).

[Terry_ALE]

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@chlh wrote:

Thank you.

The FIFO is 16383 elements. The capturing is based on a digital trigger.

I just tried again with smaller size FIFO and it works. Now I wonder how it works... Can you refer me to the material that talks about how the FIFO size may affect run time? I do not remember this is explicitly said in the guides from the NI (maybe I did not read much enough).

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Glad to hear.

Not sure of a reference that would tell you just that.  The best free reference is https://www.ni.com/en/support/documentation/supplemental/13/the-ni-labview-high-performance-fpga-dev....

I checked google and ChatGPT, none of their responses or references gave what you ask for.  If you find something, please post here.

[Intaris]

non-diagram components can often be rounding issues, concatenation or coercion effects which are automatically inserted by LabVIEW but do not have explicit diagram components to visualise it.

I notice your FIFO has a coercion dot, meaning the datatype is not the same as your data. This is visible on both sides of your FIFO. I wonder if it's coercing an I32 to U32?

It's also sometimes interesting to actually click on the non-diagram components. You get to learn the naming schemes to give yourself an idea on what it might be.

[chlh]

Thank you so much.

I will post it if I find something related.

[chlh]

Thank you for the comments.

Yes the data types there are different. I will try to match the datatype as well. It would be interesting to see how much time difference it makes. 

Reading the messages from non-diagram components always makes me headache. I can only tell somehow what components are about, but never I dig into further. Now I got interested to it.