[fpga] DRAM acces in FPGA_VI

[mhed]

Hi,

i want to use the DRAM on the card 7962R in a very simple way.

But, i miss something because when i want to simulate this little VI, i've an error from Modelsim.

The goal of the VI is made an addition with the two inputs value and store this result in memory. Then read the memory at the same address.

Here's the VI i've created :

I think there is a problem with the interaction between the DRAM access (write/request/retrieve) but i don't know where.

Thanks for your help.

[Laurent_Vaylet]

Hello,

Could you give more details about the error you get in ModelSim? A screenshot, for example ?

Also, have to tried to execute this VI without ModelSim? For instance, you can use the "Development Computer with Simulated I/O" option in the "Execute VI on" menu item.

Finally, could you provide the VI itself so I can have a look at it?

Thank you,

LaurentV

[mhed]

Hello,

It seems that i've got an infinite loop and modelsim stop due to this.

I've modified my VI to read and write only when Host provide order. It works.

But, in my final app, the goal is to write data in memory during acquisition and read only once after the end of acquisition.