fpga subvi question

[sbailey64]

I would like to develop several, custom FPGA subvis and have them available for call from a non-FPGA, host VI. Apparently, one has to first create a parent FPGA vi, put all the subvis in you plan to call, and then compile this parent. My question then is how does one call the individual subvis from a host now that the subvis are hidden in a parent vi?

Thanks,

Steve

[dkfire]

FPGA code don't work like a cpu or PC.

You can not call different code i a FPGA, all code compiled for FPGA will run on the FPGA. 

What are you planing to do ?

[cirrusio]

Steve,

This is not possible as you are programming in hardware.  If the subvi is intended to act as a standalone occasionally, then you will have to recompile each time you wish to use the stand alone VI.  However, if you just need to be able to change attributes of the subvi as the parent is running, put in controls that in the parent which have direct access to the individual subvi's you wish to manipulate.  I am guessing you have seen these articles, but if you haven't, here are two that might be of interest:

• Can I get a reference to a subvi that is running in FPGA?
• FPGA development tips that will save you time

Hope these are some help.  

Peace, Matt 

[sbailey64]

Hi Matt,

I have written a custom, gated counter running at a derived clock speed of 200 Mhz. It works as planned as a subvi where I can set various parameters before it executes via either a Windows VI or Realtime VI.  I would like to add other custom, FPGA subvis to the mix. I do not want them to selectively run...I want them to run in parallel. It would be nice if I could set various parameters for each subvi like I do with my single subvi. 

The Labview, FPGA docs state if I want to use mulitple, FPGA subvis...I will have to put them in a parent VI, then compile. However, I then seem to loose the ability to set parameters for each subvi. Does this make more sense now?

Thanks,

Steve

[cirrusio]

Gotcha.  So, you have FP objects for which you can manipulate the subvis, but when you attempt to change an attribute for one of the subvis, you get no response?  That is odd.  Is it possible to post the project containing the FPGA VIs?  Have you tried executing the FPGA on the desktop and debugging there?

Cheers, Matt

 

[sbailey]

Hi Matt,

Lets say ultimately I need to develop 5 FPGA subvis that run in parallel. I'd like to initialize them through their respective front panel connectors. If I combine the 5 subvis into a parent, I either loose access to each subvi's front panel or I make front panel connections from each subvi to the parent vi. This seems like a messy solution. What if I were developing 10 FPGA subvis I wanted to combine. I would run out of front panel connections in the parent vi.

Steve

[cirrusio]

Steve,

Whether you run out of FP connectors will depend on what the application is (how many logical slices will the FPGA consume) and the device you are running on (i.e. how much space is available on the device itself).  Unfortunately, since this is on hardware, you can not gain direct access to the subvi's themselves (so ultimately you will have to go through the FP on the host).  So it seems that the first answer to your original question is that you can not directly access the subvis - you must do this through the front panel of the parent vi.

Now the second problem is that you are having a problem with being able to set parameters for the individual subvis?  This problem (if you have FP objects set up to handle this interaction) seems like a bigger issue and one that can only be solved if we can take a peek at your VI.

Matt 

[sbailey]

Ok Matt,

Would it then make sense for me in my parent, FPGA vi to create an array that holds (or wires) all the subvi FP connections into a single entity (the array). That way, I can greatly reduce what the parent vi presents (via its FP) to VI's outside the FPGA domain?

Steve

[cirrusio]

Steve,

Consider possibly a cluster.  From the following article: 

Eliminate Arrays on the Front Panel
Arrays on the front panel take up extraordinary amounts of room on the chip as double buffering is required on the FPGA. Front Panel arrays and indicators can be replaced with DMA FIFOs, Block memory instantiation, look up tables, or block diagram constants.

I think that however you decide to do it will depend on the case.  Without further knowledge of the problem, I think I am at an end.

Cheers, Steve - hope all goes well in FPGA land.  

[sbailey]

Thanks Matt for your help. This problem is evolving. What started out as a data acquistion system for a laser instrument using the Scan Mode in the CompactRIO has turned into something more custom. I need the ability to gate a counter in 5ns increments, I need access to the remaining C modules, and I need the ability to write an interface for the NI 9870...which is not supported in the Scan Mode.

Anyway, I am new to Labview and FPGAs...so our advice is welcome.

Cheers,

Steve