06-20-2012 03:29 AM
Hi everybody,
I want to implement Watchdog in FPGA to my cRIO 9075. I already have watchdog in my RT. But when it restart after timeout, it does not restart FPGA. I have while loop in FPGA VI and i need watchdog to restart FPGA if it blocks somewhere.
Thank you
Regards
06-28-2012 06:02 AM
You can configure the behaviour of the FPGAs bitfile loading under the RIO Device Setup (right-click the FPGA in the project).
Christian