LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

fpga watchdog timeout

Hi everybody,

 

 I want to implement Watchdog in FPGA to my cRIO 9075. I already have watchdog in my RT. But when it restart after timeout, it does not restart FPGA. I have while loop in FPGA VI and i need watchdog to restart FPGA if it blocks somewhere.

 

Thank you

Regards

 

0 Kudos
Message 1 of 2
(2,750 Views)

You can configure the behaviour of the FPGAs bitfile loading under the RIO Device Setup (right-click the FPGA in the project).

 

Christian

0 Kudos
Message 2 of 2
(2,710 Views)