11-28-2014 01:30 AM
Hi.
I am using cRIO 9012 and cRIO 9114 for chassis with LabVIEW 2013.
I got this error while a new FPGA project.
Can anybody tell me what should I do?
Thank You.
11-28-2014 03:15 AM
Have you given static IP? Give static IP and check. l
i.e cRIO 192.168.0.2 and computer 192.168.0.1.
11-30-2014 08:28 PM
@PBP wrote:
Have you given static IP? Give static IP and check. l
i.e cRIO 192.168.0.2 and computer 192.168.0.1.
Hi PBP..
@I've tried both..give static IP @ DHCP..
i.e: cRIO 169.254.4.42 and computer 169.254.4.26..
but, still it shows this error.
I've checked in NI max, the connection is all right (connected-running)..
fyi, i've build a fpga project before and there's no problem at all..
but,when i'm trying to build a new fpga project,the error is pop up..
besides that, i can't run my previous fpga project anymore since it shows error-63043.
11-30-2014 10:58 PM
Can you please attach screen shot of FPGA VI block diagram?
Have recompiled your FPGA VI?
12-01-2014 12:32 AM
@PBP wrote:
Can you please attach screen shot of FPGA VI block diagram?
Have recompiled your FPGA VI?
Here are the attachements of the screen shot of my FPGA block diagram..
Yes, I've tried to recompile but then it shows error-63043..
12-01-2014 01:32 AM - edited 12-01-2014 01:34 AM
Can you put some delays in every loop? How much is your sample rate?
You have not connected delay teminal to wait until... function.
You can also combine voltage and current loop if all have same sampling rate.
12-01-2014 01:56 AM
Hi PBP..
Good news! I've succesfully deployed the VI to the real time target and can build the new fpga project without an error.
I believed it caused by the processor overuse .
so, i decided to uninstall some of the unused software to the controller.
Btw, I thank you very much for your help. Really appreciate that..
12-01-2014 04:26 AM
Great.
Thanks for kudos....
If you put some delays in loop this will allow processor to do other task. 🙂
12-01-2014 08:08 AM
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