generation and acquisition

[Salvio]

nothing to do...i've tried as u have suggest to me but it doesn't work...can u see this my new VI and try to correct it?
tnx really tnx

[Salvio]

sorry it wasn't my file this is the right file

[Salvio]

Nothing?nobody can help me plz?

[Salvio]

another thing that i've seen is that to compile my VI the cRIO's memory go under 50% and it doesn't work very well...
plz help me and tnx for any replies.

[JMota]

I ran your VI, and after placing a probe on the error wires for the acquisition loop, I saw error -50352 "The requested memory could not be allocated." being generated by the FIFOA.Start node. This is probably because you are asking for a 3,000,000 elements FIFO depth. Have you tried getting rid of the FIFO.Configure, FIFO.Start and FIFO.Stop nodes, so that LV can use default parameters? I just tried it and now I see both graphs live.

Additionally, I noticed that you are not closing the FPGA reference, which leads to leaking References. You should add a Close FPGA Reference node outside of both of your loops, and get it to execute once both loops have been stopped (you can simply merge the errors from both loops and wire the error out of the merge errors node into the Close FPGA Reference node).

Also, you may want to slow down your acquisition rate just to make sure you can acquire data at a slow rate.

Good luck.

JMota

[Salvio]

i've eliminated the Fifo start and fifo configure and i've tryed to put an FPGA stop but what i see is that  the cRIO doesn't empty the the buffer while he is acquiring and sometimes he stops the VI because he takes  too much memory i think. can u show me how to correct it?
i post the VI that i've correct.

[Salvio]

I mean now with this VI i can generate and stop the generation and generate again but i can't do the same with the acquisition.
In fact if i start with generation and after a while i want to acquire a signal it works, but if i stop the generation and the acquisition and then i want to generate again and acquire again i'm able only to generate but i don't acquire nothing...why?

[Salvio]

JMota can you help me plz?

[JMota]

Hi Salvio,

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@Salvio wrote:
I mean now with this VI i can generate and stop the generation and generate again but i can't do the same with the acquisition.
In fact if i start with generation and after a while i want to acquire a signal it works, but if i stop the generation and the acquisition and then i want to generate again and acquire again i'm able only to generate but i don't acquire nothing...why?

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If I understand correctly your problem, generation works with no problem, but acquisition is the one that is giving you some trouble. What exactly does it mean that you don't acquire anything? Is it that you are getting bogus data back (~0) or that the application actually gets hung?

This is what I initially thought your problem was, but after a second look to your host VI I noticed some other things that could also be causing trouble.

I think the problem you are experiencing is because there is something wrong with the DMA FIFO synchronization. The second time you try to run the acquisition, the DMA FIFO has some elements from the last acquistion, since you do not guarantee that the DMA FIFO will be empty next time you start a new acquisition cycle. What I suggest you do, is that once you are done with an acquisition, you do clear the DMA FIFO by reading and dismissing all elements available in the FIFO, that is, until the "Elements remaining" output says zero. I believe one of the DMA FIFO examples that ship with NI-RIO do this, but I'm not 100% possitive.

I don't see why you need to execute the Run method everytime you write info to a different address. You should look into the Synchronization examples as to how to synchronize communication between the FPGA and the Host VI. To simplify your loops, I suggest you move all the code that passes data down to the FPGA into different loops in the Host and FPGA VIs. The most interesting thing that could be messing up things, is the execution of the "Reset" method in the host when you are done generating. That will reset the whole FPGA VI, so it will interrupt any code being executed in the FPGA or invalidate communication from the Host to the FPGA. I suggest you re-think the use of the Reset node or do not use it if you don't need to.

Although you do pass errors around, you don't display them anywhere, so it is possible that you are missing the error reporting the Nodes provide. For debugging purposes, I suggest you create and wire some error indicators to get status of your loops.

Last note, the way you are closing the FPGA reference is not very clean, since if you stop just the acqusition or the generation loops, that will close the fpga reference will invalidate the reference in the other loop. You should be waiting until both loops complete to execute.

Regards,

JMota

[Salvio]

Hi JMota. Tnx for the reply.
i've eliminated the Reset Node but i've got some problem to reset the elements remaining in the FIFO. how can i reset them when i stop the acquisition?
tnx again