how many gates for a PID loop?

[mwm]

I'm considering using a NI FPGA such as the PCI-7831R to implement in parallel several PID loops.  I'm having a hard time figuring out just how much "space" (in terms of gates) a PID loop uses, and thus how many can be fit onto a given FPGA.  Reading the FPGA Module user manual didn't help, it just made me scared, because there are so many warnings: "don't do this, it will take up too much space!"  If someone could explain how to estimate the gate requirements for typical operations, that would be great.

Thanks!
-MWM

[Richard P.]

The space and time efficiency of your code is widely under your control, and since our compiler will ptimize your code for speed, it is hard to say how much space a given loop will take. How many loops do you need to have running simultaneously? We can try to give you an answer as to possible or impossible.

[mwm]

Ok, a few possible scenarios:

1) 8 basic analog PIDs running simultaneously: reading from the ADCs and writing to the DACs, no communications with the host computer, all PID parameters static.

2) same as 1), but with PID parameters (gains, time-constants) dynamic, supplied by the host computer's VI.

3) same as 2), but with reporting to the host computer's VI of the ADC readings and DAC outputs.

Is it possible that these PIDs would *not* run at the full speed of the ADCs ? If so, I would want to know that, too.

Thanks,
-Morgan

Richard wrote:

> The space and time efficiency of your code is widely under your control, and since our compiler will
> ptimize your code for speed, it is hard to say how much space a given loop will take. How many loops
> do you need to have running simultaneously? We can try to give you an answer as to possible or
> impossible.

[Richard P.]

Your application sounds reasonable in all 3 instances. Take a look at this document:

http://zone.ni.com/devzone/conceptd.nsf/webmain/8E999A74E43AC76186256F5E0068CFAC

This link leads to a tutorial on high-speed data acquisition with cRIO, specifically a 9215.
It is possible that the loops in which you acquire analog samples will not run at the full speed of the ADC's on the module. These speeds are the maximum and your speeds will depend on the nature of your programming.

Here is an even more in-depth look at cRIO development:
http://zone.ni.com/devzone/conceptd.nsf/webmain/62B388DB80B557028625703700639B89


Richard