how to control the time delay between two channels? (5640R FPGA)

[niton]

I use two DACs to transmit a modulated RF signal simultaneously.

But there is a time delay between two RF signals. Every time I stop and start the Host VI, the delay time changes.

I want to know why there is a delay and how to control the time delay between two channels?

The attched are the Host VI. The FPGA VI uses DAC_0_Port_A_Clk and DAC_1_Port_A_Clk as the base clk of timed-loop. All of  them in FPGA  are idential.

Thanks!

[JVP]

Hi Niton,

I have a few questions for you, as well as few troubleshooting steps I need you to try.

1) What version of LabVIEW are you using?

2) What version of the 5640r drivers do you have installed?

3) How are you measuring the time delay?

4) I would like for you to run a shipping example that acquires on both AI channels synchronously.

    - The example is called "ni5640R Dual Channel Analog Input and Output".

5) In your post all I see is the two images. Would you mind posting the code so I can test it on my end please.

Best Regards,

Jignesh P

Applications Engineer

[JVP]

Hi niton,

I have few more questions for you.

1) What are you needing to be synced exactly?

2) Do you need the signals to be phase locked?

3) What delay values are you seeing between the two DAC's?

4) What is the level of sychronization that you expect/require?

Best Regards,

Jignesh P

Applications Engineer

[niton]

Hi,Jignesh P

the problem has been solved. the reason is there are two resets in two channels. they can not be sychronized in us level.

using only one reset to control two channels can solve this problem.

thank you all the same.

niton