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polymorphic VI on FPGA

I ran into an unexpectred problem yesterday.

 

I had created a polymorphic VI for taking care of encoding and decoding of information being sent via a 64-bit DMA to a FPGA program.

 

When I replaced the individual VIs with my new shiny Polymorphic VI I got errors on the FPGA.  None of the INSTANCES of the Polymorphic VI being used inthe FPGA code were a problem, it was the UNUSED Polymorphic VI instances which were causing me headaches (which were essentially intended to be used on the host).

 

I was unaware of this and wanted to ask quickly if this is intended, required or even possible to change.

 

I know that when we compile we can choose to remove unused polymorphic instances.  Should this option allow me to compile?

 

Shane.

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hi Intaris,

 

This is Kais from NI Germany. Can you send us a simple FPGA Project where we can reproduce the issue?

I have added a simple Polymorphic Project to the attachment, can you test this Project on Host and later deploy it on your FPGA Target?

 

 

 

Kais Mekacher
Applications Engineer
Germany - Munich
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I am using LV 2011.  Could you back-save?

 

Shane

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Never mind I fired up a VM with LV 2012.

 

Of course the polymorphic VIs you have there don't show a problem because they're not part of a FPGA target.

 

Simply add an FPGA target to the project and place the polymorphic VI in a VI there.  You will see that it is broken.
  Even if you select only the first instance.

 

This is because the second (unselected) instance is not compatible with FPGA coding.

 

Oh, and change all controls and constants from DBL (Which are not cupported on FPGA) to SGL.

 

Shane.

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Hi,

 

Tomorrow I will try to test the Project on FPGA Target and tell you the Final Result.

 

Best Regards

Kais Mekacher
Applications Engineer
Germany - Munich
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Hi,

 

so I try the project on FPGA and I did reproduce the Issue. This is not a BUG on FPGA.

Numeric or double is  not supported in current target. You should change the representation to FXP. See Screenshots1.

 

The same is with Arrays. Arrays on FPGa must be fixed size.

I add a sample Project here to see how to work with Array on FPGA.

 

Search 1D Array on FPGA

https://decibel.ni.com/content/docs/DOC-22164

 

I hope that is clear now why it doesn't work.

 

Best Regards

Kais Mekacher
Applications Engineer
Germany - Munich
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If you are new on FPGA, this is a good Link to Start:

 

LabVIEW FPGA Module Training

http://www.ni.com/white-paper/3555/en

Kais Mekacher
Applications Engineer
Germany - Munich
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Message 7 of 36
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Erm, I don't mean to be rude but the DBLs are from YOUR code, not mine.  The poroject linked in this thread was posted by YOU, it is not my code.

 

I also mentioned in my previous post that the DBLs need to be changed to SGL if the code is to work at all.  So in essence you are now giving yourself feedback on what was done wrong with the code you have posted.  I would like very much (if you don't mind) to get back on topic with my problem which is really unrelated to what you have just posted.

 

To make things easier I'll take the time to get the example fixed for you so that you can pass it on to someone to clarify issues.

 

Shane

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Hi,

 

Yes the Example was mine, but it was tested on the Host, not FPGA.

 

Can you post me your Demo Project, so i try it on my FPGA Target?

 

Thanks

Kais Mekacher
Applications Engineer
Germany - Munich
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Message 9 of 36
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It is included in my last post.

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