set sampling rate as 25 ns...

[davut]

Hi,

I m trying to test sampling rate of cRIO chassis 9103..

I created a simple FPGA project, for sampling signs that FPGA clock frequency equal to 40 Mhz (on board default value). I applied 1 Mhz square wave to DIO6/SPI MISO pin, place one of the slots of chassis ... I set one tick 'loop timer' in 'for' loop, for every sampling moment (totally 32 sample point).

the input signals one cycle = 1000 ns (1MHz) and i m planning to see samples every 25 ns (40 MHz) on waveform Graph. But the graph shows me just 10 points for 1 cycle like taking samples every 100 ns instead of 25ns. (FrontSamplingRateObservation.png )

is it what has to be? if yes, how can i get faster the sampling ratio..

I attached .vi pictures  of the project..

[falkpl · Accepted solution]

you might consider the single cycle timed loop and pipline the operation.

[viScience]

Just read the DI in a for loop and let it build the array for you.  Set your clock ticks to 1 and make sure the FPGA target clock is set to 40MHz.  You might also try creating a derived 80MHz clock and see if your DI input will sample that fast, it depends on the hardware.

[davut]

thanks for your suggestions..

i try to decrease work-load in 'for' loop and also rebuilt diagram using SCTL.. optimizing 'for' loop increase the performance, but using SCTL is sampled as i needed, optimum..

i tried several applications to apply SCTL loop in simple way..

first i tried to implement SCTL using 'enable Indexing' feature.. But it give me an error as "Arrays must be fix size" .. (enableIndexing.png)

on my second approach, i define the array, outside of SCTL and used 'replace array subset' block as shown in 'replaceArraySubset.png'.. There wasn't any broke arrow and compiled, unfortunately, when running the project, .vi is freezing.. in my opinion, inside the SCTL is taking more than one cycle..

as a solution, i built block diagram in flat sequence.. and it s worked..(StackedSequenceStructure.png)

 i wondered, is there any more simple block diagram for same process..

thanks again..

[Allison_M]

Hi Davut,

It's really hard to tell exactly what you are trying to do from just the .png image attached. We generally don't recommend using stacked sequence structures for this very reason; it's very hard to see the code. You should be able to replicate the same code by using a for loop and autoindexing to build the array.

Hope this helps,

[davut]

hi alison,

i want to use chassis slots as DI\O without any module.. when i implemented an input from my signal generator, 4Mhz square wave, i planning to see samples for every 25 ns (40MHz- chassis onboard default clock cycle). i couldn't implemented it by using 'for' or 'while' loops but SCTL struct.. It is sampling for every 25 ns by using SCTL.

Unfortunately i think i couldn't dizayn it affectively.. I tried several conbinations ('enable indexing' feature, etc...) but i couldn't..

And i wonder if there is any more simple block diagram for same process

my project file is attached... ( needed hardwares : cRIO 9004 - cRIO 9103 )

[viScience]

How about a for loop around the SCTL

[davut]

  Hi sachsm,

i think, generally, i couldn't explain it well...

i want to read DI\O every ticks. Unfortunately, it looks,  'for' and 'while' loops need 3-4 ticks for every iteration.. So, i solve the problem reading DI\O without loops, using 'Stacked Sequence Structure'.. if you open my example project I have attached last time, you will see, it doesn't look as an efficient design.. 

I only wanted to learn if there is any possibility implementing same process in a better way (using a loop that consume just one tick every iteration)..

do not spend on that topic so much time.  Thanks again..