test FXP LMS fpga

[charansai]

Hi everyone,

 I am trying to test IP Generated 'FXP LMS' on myRIO 1900. I don't know what I am doing wrong, but I am not getting any appropriate results !

 I made sure all the data types are same, I tried using ''Abort Invoke method'' also after ''Run Invoke method'' ( although VI will terminate automatically after 1 SCTL ).

 Results are proper if I am using the built in Adaptive FIlter LMS on RT side but using FPGA on RT module is what confusing to me.

Please check the VI attached below and correct me .

Thank You. 

[mateh]

Hi.

Did you try setting "Wait Until Done" to True?

Are you using the same step size as the RT filter (the default values in your VI are different)?

Are you getting any errors?

[charansai]

Hi ,

No errors, I tried setting ''wait until done'' true and I am using the same step size at both places and I compiled the FXP LMS before running on RT ! 

[charansai]

 I am now getting  ''e(n)'' value as array of 500 elements and 0,4 value and ''y(n)'' values as 500 zeros !!! Cant understand whats happening !!

[Maxe93]

Hey,

To summarize your Problem:

- When you use the FPGA code (generated with IP generator) you get two lines on the waveform graphs. (0 and 0,4)

- When you use the RT code you get two curves on the waveform graphs.

- You're expecting the same curves with the FPGA code.

Please correct me, if I'm not right.

I've just recreated your HW- and SW-Setup and I found out, if you change the 'AFT Create FIR LMS.vi' in your RT code from LMS(Real) to LMS(Complex) you get the same lines like you get with the FPGA code.

So I guess that the FPGA code works in a complex way. I don't exactly know how. 

I try to find something out about that and if there is a possibility to change the IP generated FPGA code to work real.

[charansai]

---

hey there,

I am sorry, i think you got that wrong !

AFT Create FIR LMS.vi with real ( the below code ) is giving the correct results. My problem is I could not get those results from the above code i.e by calling fpga Target.

I found a work around, like using DMAs(FIFOs) to transfer the data from Target to Host and it is working well (problem is Host to Target is not working)

But I dont know why the above code is not working .

Expected results are as presented below .png file.

Thank you. 

[Jacobson-ni]

Charansai,

I'm glad that you were able to find a workaround for the time being, but if you are still concerned with finding out why your original code was not working or if the workaround you described is not a suitable long term solution, I would be interested in knowing the following.

1. What version of LabVIEW are you using? This will let us accurately reproduce your system as some VIs or Xilinx IP might have changed.

2. Thank you for replying with what the expected results look like, can you also show us the results from runniing the first VI you attached.

3. If you could attach your FPGA application, or better yet, the project where you see this behavior, we would be able to better look at what is happening. Combined with an image of the outputs you are seeing we should be able to reproduce your system accurately.

4. How are you configuring the Xilinx FXP LMS?

From what I understand, it sounds like you are seeing expected results from the RT VI but not your FPGA. If you are using Xilinx IP I would take a look at the documentation of the IP to make sure you are following their suggestions.

http://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_1/pg149-fir-compiler.pd...

My gut feeling is that there is something off with the RT implementation of the FPGA code. I would always suggest using a DMA FIFO to move the data you are looking at but without the code I cannot tell if what you are doing will work. As a side note though you can just have the Run method outside of the for loop, if the FPGA applicaion is already running, that method will not do anything.

[charansai]

Hello Jacobson,

Thanks for your concern. My work around is flawed one, I am still very much interested in solution to my problem.

1. I am using LabVIEW 2015 and myRIO 1900.

2. check for png1

3. I didn't get your point clearly, my fpga application is 'Active Noise Cancellation'

4. I only changed Step Size Integer word length from -2 bits to 1 bit, rest all are default values. Please check png2

Yes, the results from 'RT side LMS' is quite good. Whereas, if I call 'fpga LMS' results are bizarre.

In my work around I used DMA FIFOs but data transfer from Host to Target is not working, where as Target to Host is working properly. Looking at the comments of this tutorial [ http://www.ni.com/tutorial/4534/en/ ], I am considering there is some problem with Host to Target data transfer.

[charansai]

Cont.d

My work around: I created two memory elements with intial values and size same as the intialize arrays in the given VI. I applied LMS on FPGA side and  wrote the result values (y and e) to FIFOs and I read these values on RT side. It is working well but  as I said, its flawed, I cant go on changing intial values of memories every time. I could get over this problem if Host to Target data transfer is working properly.

I will attach the work around VI as well below and Its results in png 3.

Finally, I am not running the FXP LMS vi continuously on fpga side. My intention is FXP LMS has to take input, run and give output through read for each iteration, so I kept run method inside for loop.

Thank you again

[Jacobson-ni]

While I was looking into this I realized I was looking into some FPGA code that Max (posted earlier on this thread) gave me to show what the issue was and realized that you had never explicitly posted the code that contained the FXP LMS filter that you are using.

Could you post the code of the FXP LMS filter you are using or tell me exactly how to generate what you have? I pointed to the Xilinx IP earlier but now that I look at everything again, I do not think that you are using the Xilinx FIR filter.