time violation and argument 'or'

[granix]

hi, i was getting a compile error as below :

Device Utilization Summary:

   Number of BUFGMUXs                        2 out of 16     12%

   Number of External IOBs                 242 out of 484    50%

      Number of LOCed IOBs                 242 out of 242   100%

   Number of MULT18X18s                     64 out of 96     66%

   Number of SLICEs                      10761 out of 14336  75%

Clock Rates: (Requested rates are adjusted for jitter and accuracy)

  Base clock: 40 MHz Onboard Clock

      Requested Rate:      40.408938MHz

      Achieved Rate:       33.812342MHz    <<<=== Timing Violation

Enclosed vi as below.What could be the reasons for such error ?

And another one is as below with enclosed vi ( error : argument 'or' must have the same length ).

What is the problems ?

Hope you guys can help...thanks a lot.

[granix]

i had modify the code for find_max.vi but it came out :

ERROR:HDLParsers:3367 - "C:/NIFPGA85/srvrTmp/LOCALH~1/FPDE17~1/bushold.vhd" Line 358. 95999 is not included in the index range, 30463 downto 0, of array Clk40WideDataIn.

Any idea what's going on ?

 

[Van_L]

Hi Granix,

I took a look at your vi, one thing you must chage on your find_max2.v.
You got an array of size 1500 on the front panel.

Please take a look at this to optimize your code first

What FPGA system are  you using? cRIO? RT target?

[Van_L]

Hi Granix,

The reason your testing.vi is causing Timing Violation is because the execution of your while loop actually takes longer than desired, in this case it is requested to perform at 40MHz but it is truly operating at a maximum rate of 33.8MHz which is slowed down by the longest path of the vi.

To optimize your code to speed up the execution to meet the 40MHz spec try the following:

Fixed point operation: when you multiply fixed points the output of the operator actually allocates more bits to prevent data loss. For example, mulitplying 2 32bit fixed point values would generate a 64 bit fixed point output and the larger the data type, the longer it takes to execute. To prevent this, you can right click on the operator>>properties>>uncheck "adapt to source". Detailed information about fixed point and overflow can be found here.

This is also very good to look at to optimize FGPA code

[granix]

hi Van_L ,

u mean that 1500 elements is over-sized? is it that using handshaking to overcome this problem ? or else any idea ?

10x for helping out.

[granix]

btw, i'm using PXI-7833R

[Yi Y]

Hi Granix,
Van is out of the office today and I will address your question. For the find_max.vi, please replace the 1500 element front panel array with either LUT if you are not changing the content of the array or use DMA if you are transfering the data from your host to your FPGA target. That should take care of the compile issue.
I compiled your test.vi and I'm also getting timing violation error. Typically you should not receive timing violation error unless you are using SCTL or loop timer. I need to do a little more research on it to determine the cause of the error. Meanwhile, try to optimize your code according to the pages Van suggested, remove as many front panel objects (specifically, reduce the number and size of the arrays) as possible and reduce the number of multipliers might also help.
Please post here if you have any questions.

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support

[granix]

Hi,

i had found a DMA tutorial on http://zone.ni.com/devzone/cda/tut/p/id/4534, but seems that this tutorial does not fit in LabView 8.5. It only show how to past arrays into host, but how to past data from host to target ?

Enclosed host3.vi and find_max_2.vi and trying to past array from host to target. Upper loop seems running but it give out funny result, not a complete array. how to make sure the target receive a compleate array before it process it ?

my concern is to past an array into target and find its max point.

thanks for the guidance.

[Yi Y]

Hi Granix,
To pass data from host to target, change your FIFO type to "Host to Target". You need to check on the FPGA target side of the FIFO is full and check on the host side if the buffer is empty to make sure there's no buffer underflow and overflow issues. Refer to this article with more information about how to write from host. Also refer to Basic DMA Output - R Series.lvproj in the example finder (Help->Find Examples...) for the code to transfer data from host to target.
Regarding the compilation that failure for test.vi, it's due to the fact that the fixed point input for your multiplication operations are too large. Normally, the primative functions (multiplication, add, subtract, etc) should execute in one clock cycle. When it comes to fixed point input and multiplication, however, the output of the multiplication adapts to the size of the input. So if the input is too large, the multiplication operation ends up taking longer than one clock cycle to execute, and cause the compilation to fail timing.
The solution is either reduce the input and output size of the multiplication functions (refer to Van's post to reduce the input and output size of your fixed point multiplication functions). If you do not want to reduce your input and output size (for maximum precision), you can download the Fixed Point Math Library, and use the math library's multiplication function, which allows you to pipeline your multiplication operation and set it to complete in more than 1 clock cycle.
Hope this helps.

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support

Message Edited by Support on 05-26-2009 09:15 AM