Storing an image in DRAM on an FPGA

[nissen6]

I have an image processing function that looks at the difference between the current image and a reference image stored earlier. I am trying to implement this calculation on an FPGA but I'm having trouble with recalling the stored image from DRAM at 100 MHz. It seems to only be able to recall every other pixel and even then the values that come back are offset randomly. I'm using a PXIe-7966R with a NI-1483 capture card. Is it possible to access DRAM at 100 MHz?

[the_mitten]

Hi Nissen6,

Could you share the code you are using to access the DRAM? I'd like to clarify how you are reading/writing to the DRAM so that we can get a clearer idea of what's going on.

Regards,

[AmitShachaf]

Hi,

I am using NI PCIe-1473R and storing images in DRAM.

What is your pixel rate? How many bits per pixel?

[nissen6]

This is what my write and read code looks like. The read image does not read back fast enough so the retrieved image is missing a lot of data.

[AmitShachaf]

What is your data rate?

Image size? Bit depth? FPS?

How many DRAM memory banks are you using in your code?

[AmitShachaf]

Do you pack / unpack your pixels before accessing DRAM? It is not clear from your VI if you are using 64 bit data.

You should use 64 bit or 128 bit access to DRAM. You need to pack / unpack the bits in that case.

[mesolmaz]

Hi Amit,

I need to transfer and store a single image in DRAM from PC, for image background subtraction purposes. I will use this image in DRAM to do subtraction in real-time from CameraLink camera. I am using the 10-tap 8-bit DRAM example from NI as my base case. 

I dont see how I can access certain addresses using CLIP? Even in this example, there is no direct access to certain locations on the DRAM, just the banks.

[David-A]

The FlexRIO driver installs an example that demonstrates how to perform random access on dram using the memory IDL and a sequence of counters. It demonstrates this by writing an image to DRAM, then reading that image back in orientation that is either mirrored, rotated, or some combination of both. Here is a screen shot of the host vi after the sample image has been loaded to DRAM, then read back such that it appears mirrored and rotated -90 degrees. 

If the FlexRIO driver has been installed, you can access this example by opening the example finder and nagivating to Hardware Input and Output>>FlexRIO>>External Memory>>Random Access Pattern - Memory IDL.

[mesolmaz]

Hi David,

Thank you for the response. I am not sure if I can use this example in my code. I am using NI-1473R-LX110 as my FPGA board and the base example is 10-Tap 8-Bit Camera with DRAM. In this example, there is no defining the address to place the bytes of data. It just uses the banks of DRAM to store intermediate data. 

Can you please comment if I can use the principle in this example for NI-1473R-LX110?

Mehmet

[David-A]

Sorry, I didn't realize this was an older thread with multiple questions. I thought you were the OP who said they were using a flexrio board with a FAM frame grabber. 

I'm unfamiliar with the 1473R. If doesn't give you access to the DRAM from the block diagram via a memory item then you won't be able to use the example I referenced.