Motion Control and Motor Drives

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real time target & fpga

Hi all,
I am working on real time motion control of a dc motor. I have a main computer and a real time desktop target which has a fpga card.
I use the fpga to do the encoder quadrature decoding and also for sending the analog signal to the motor drives. My real time desktop target gets the motor position and generates pid control action. Then, the control signal is send to the amplifiers using the fpga card. The problem is as follows:
The vi running in the fpga is in a timed loop of 40kHz. The pid controller vi runs at the desktop at 1 kHz. I use a timed loop and see that the loop completed in that desired frequency. However, when I just try to log the data, it is very slow, it just does not show the changes in the input and output at every milisecond. For instance, when the graph does not show all the points either. On the other hand, the loop does not finish late at all. It just works fine. I could not find out the problem. Since I read only one point from the fpga at every milisecond, I did not use any of the FIFO block at all. I did not need any buffering... What could be the problem be? How can I just read the input\oupput at every milisecond?totally annoying. Even, if I press stop control butten for the timed loop, it just takes a while to stop the control loop as well. I would be happy if you could give a response.

thank you.

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Without knowing the exact architecture of your application it's a bit hard to give you a good advice but here are some things you should check:

  1. First you should make sure that the data logging part and the control part run in different threads. E. g. you could use two vis and configure one (the control vi) for time critical priority. This vi should communicate with the data logging vi through real-time FIFOs.

  2. How is the CPU usage of your application on the RT target? If it's close to 100% non-time-critical processes might get starved.

  3. Have you already followed these hints for optimizing file I/O on an RT target?

  4. Depending on your implementation it might be necessary to synchronize the RT and FPGA vis. This can be done by using interrupts.


I'm not sure if I have really hit the core problem. Please provide some source code, screenshots and so on to help us to identify the issue correctly.

Thanks,

Jochen Klier
National Instruments Germany

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