Update rates on analog outs M-series

[marcelpicard]

Hello, I am using an PCI-6229 (M-series) and I am interested how the 4 analog outs work. Im especially interested in the fact that in the user´s guide is written that all analog out channel use one FIFO. How does that work exactly? For only one channel usage the update rate is up to 833 kS/sec, but for 4 channels the update rate is 625 kS/sec. I am worried about the fact that if I divide the 833kS/sec into 4 same rates for each channel I got a higher rate per channel (208.25 kS/sec). I hope somebody read this and can explain it to me, how this works.

[RamonaL]

Hi Marcel,

this has nothing to do with the FIFO. The important parte is the Multiplexer that is used to output the data to the diffrent channels.
So you can output with 4 channels less data, because the multiplexer needs this time to switch between the channels. And this takes is quite fast, so the calculation you did, doesnt work this way.

Hope this helps,
RMathews

[Mcdan]

Hi Marcel,

You are correct that if you have multiple analog output channels doing hardware timed generation, then they all share the same FIFO.  For this type of setup, all channels would be in the same DAQmx task.  Because of this, the driver is aware of what order the channels are written to, and can ensure that data arrives in the FIFO in the correct order.  For instance if you have channels ao0,ao2,ao1 in your task, DAQmx will ensure that data is transferred to the FIFO in that order.  Each sample clock, every AO Channel updates and the hardware goes about loading the DACs with new data (please note, there is no multiplexer for analog output... each channel has its own independent DAC).  To do this, data is read from the FIFO and written to the correct DAC.  The issue here is that data must be read out of the FIFO and written to every channel before the next sample clock arrives.  The more channels you have in your task, the longer this process will take.  This is why you see the max rate decline as more channels are added.

I hope that helps,

Dan

[marcelpicard]

Hi Dan!

That means that for example a sinewave is generated on a0 for the first sample period and the system is able to generate a second one on channel a1 and so on. Does the other channels have any signal if a0 is getting the sampling block from the FIFO?

Greetings

Marcel

[stilly32]

Hey Marcel,

For M-Series, all 4 DACs share the same FIFO, data transfer bus and output clock. So if you are generating on all four channels, a sample is sent to DAC1 and latched in, then samples are sent to the rest in the same manor. All four DACs then generate on the same output clock. While the DACs are loaded with new values they retain the value from their previous update.  

The important takeway is that all output channels are updated on the same clock - even if the transfer from the FIFO occurs at different times. Hope this helps,

Andrew S

Multifunction DAQ Product Support Engineer

Message Edited by stilly32 on 05-16-2008 10:18 AM