07-12-2021 09:19 AM
I don't think I understand quite what you're asking or what you're trying to do. Counters are very flexible which is pretty great, but because there are so many ways to work with them, it's especially important to have a very clear understanding of your measurement and generation needs in order to give the best advice.
Can you describe more about *what* you want to do without getting into details about *how* you think it would be implemented? Try to describe what you'd like to do without using any of the following specific terms: "gate", "sample clock", "frequency division", "pause trigger", "start trigger". I think that might help.
-Kevin P
07-12-2021 10:15 PM - edited 07-12-2021 10:19 PM
Hi Kevin
Thannk you for your reply!
I draw a signal relation sequence diagram(named Question_Reply.jpg) for you to understand my problem.According to the user manual,i think gate signal can realize this function.
Can i use the 'sample clock' of Counter to finish this function?
In the same time,I have two questions about Counter sample clock.
clock.Relation doucment is in the Compressed package(named Counter_Sample_Clock).
Firstly,
I usually use counter output in implicfit mode instead of sample clock.
i use the program fraction 'Counter test 1' as the external sample clock,I use the program fraction 'Counter test 2' to out pulse signal with the 'Counter Test 1'
i am very curious that what the function of counter sample clock.
in my opion,i think that daq will out the pulses that i defined(i determine the high time and low time of pulses) on the rising edge of sample clock(Source is external signal).is my idea right?
because i think the sample clock function will connect the external signal to the Gate signal to controll the pulse signal generation.
And i think if i connect the source of the sample clock to the external signal when i out signal ,the rate of sample clock is no useful.Is my idea right?
Secondly,
Also ,i discover a abnormal phenonmenon in the 'Counter_Buffer_Continue' program fraction. when i use external clock mode but external signal do not input the NI board ,i also see the pusles generation in my wave Oscilloscope.
I think it is not a right phenonmenon.
In the same time,the program sometime have a error that‘The sampling clock pulse occurs before the pulse is generated according to the previous pulse specification.Please use a sampling clock that is slower than the pulse sequence to be generated’.
Thank you for your answer!
Yuzn
July 12 07
07-13-2021 04:11 PM
Sorry, but your questions still aren't quite clear to me and I can't interpret several details of the code screenshots. Language and translation issues I think. Your timing diagram "Question_Reply.jpg" is the most helpful. I'll try to respond primarily to that. I won't address every subtle detail here, but will try to get you close.
1. Your AO task should use the "Known External Signal" as its sample clock source, with active edge=rising.
2. I'm inclined to suggest that your "Out Signal By Counter" should be a finite retriggerable pulse train. It should trigger off the special internal signal "/Dev1/ao/SampleClock", and the finite # of pulses should be calculated to fit inside the pulse width of the "Known External Signal".
3. When you do things this way, your counter output pulse burst will naturally end after the final AO sample is generated. I think that solves your problem #3 in "Question_Reply.jpg".
As to your error in "Counter_Buffer_Continue", the board must generate every set of pulse timing parameters you give it at least once before you change to a different set of parameters. This is true whether you try to update those pulse parameters according to a sample clock or whether you run in on-demand mode without a sample clock and try to update them with a software call.
Apparently, your sample clock rate is faster than some of the pulse periods such that those pulses aren't able to complete before the next sample clock arrives. That's what causes the error.
However, I don't see anything in your "Question_Reply.jpg" diagram that explains why you might need to do this. I don't see any variable pulse frequencies nor do I see anything that might be the sample clock that initiates a change in pulse frequency.
-Kevin P
07-13-2021 09:35 PM
Hi Kevin,
Thank you for your reply!
Your answer is so helpful for me and slove my problem perfectly!
I also have a problem.
In order to help you understand my problem I also draw a Signal timing diagram(Question_Reply_2.jpg) for you!
I want use Counter 'Sample Clock' to finish this function instead of 'Implicit'.
Thank you for your answer during the busy working time !
Yuzn
July 14 2021
07-15-2021 09:31 PM
One odd quirk with counter tasks is that they can't derive their own sample clocks. They have to get them from "somewhere else". Often, that's either another counter's output pulses or the internal SampleClock signal from an analog task.
So the source terminal would need to reference some available clock signal. Sometimes the rate might not be known or it might vary. Fortunately, it's usually fine for the rate terminal to be an estimate. The role it serves is to:
- ensure a minimum buffer size when doing continuous sampling
- set the "dt" value for DAQmx waveform data when using an external sample clock. Encoder tasks do not natively return waveform data though, so this role mainly applies to analog tasks.
Having said all that, what's your reason for wanting to change output pulse timing parameters according to a sample clock? I don't see how that fits in with the other description and timing diagram you've presented. I don't think it'll work with my earlier suggestion to configure for a retriggerable finite pulse train.
-Kevin P
07-16-2021 10:09 AM - edited 07-16-2021 10:31 AM
Thank you for your reply!
In order to explain my need,I draw a picture for you!
The picture is in the attachment 'Question and Reply 4_2'.
I compare the output of analog sampling clock with that of counter sampling clock.
I use a counter to simulate the Sample Clock,and use another counter to test the CO with Sample Clock.
Yuzn
July 16 2021
07-16-2021 11:19 AM
I appreciate the efforts you're putting into these diagrams to try to help clarify the questions. But I'm still not understanding the intended timing relationship between the "Known External Signal" clock and the (apparently) variable frequency pulse train output.
Previous sketched timing diagrams showed apparently constant rate pulses only while the KES was high. That led to my suggestion #2 back in msg #13. Your scope pics show variable freq pulses whose timing has no discernible relationship to the KES.
What do you want it to look like and what purpose does that serve in your application? Why is it important to change over to sample-clock based buffered pulse output instead of using implicit timing? If that change is feasible, what signal will act as the sample clock?
Now I'll address your questions in red from Question_Reply_4_2.jpg
1. When you specify an external signal as a sample clock for your AO task, the 'Rate' input mostly doesn't matter, as you found. I talked about what role it *does* play in the middle section of my msg #15. But it's the specified external signal itself that drives sampling, whatever that signal's rate is, and regardless of how well you've estimated it with your software 'Rate' input to DAQmx Timing.
2. I'm not able to interpret key parts of your CO code but here's what I *think* I see going on. First some background that's key: pulses are defined to be in idle state first and then in active state. With the default idle state being low that means that pulses are defined by a low time followed by a high time.
Another thing to know is that when you update the pulse timing parameters for an active pulse task, they will *not* interrupt and modify a pulse that's in progress. The new timing parameters won't take effect until the present pulse is completed. If you follow your scope traces carefully, you'll see that after each sample clock rising edge, the pulse timing changes the *next* time the pulse finishes its high state.
That's why pulses don't line up with the KES. The KES is used to decide when to put new pulse timing parameters "next in line" for the task to use at its next opportunity. But the timing for that opportunity is dictated by the pulse timing parameters themselves, not the KES.
3. Once again, the 'Rate' terminal input to DAQmx Timing for your CO task is probably entirely meaningless. When you define an external signal as the sample clock, that signal gets used directly regardless of its actual rate. Neither of the 2 roles I described for the 'Rate' terminal back in msg #15 would apply to a *finite* counter output task. (In a finite task, the buffer size is determined more explicitly and does not depend on the 'Rate' terminal input.)
So your scope pics show that you *are* doing sample clocked pulse generation. And your variable freq pulses just aren't lining up nicely with your KES. Which is entirely expected as I mentioned at the end of my msg #15.
It keeps seeming like you're trying to use an unnatural combination of pause triggering, variable freq output, and sample-clock-based freq changes. Are you really sure it's necessary and if so, how and why?
-Kevin P