how can i reach the 200Mbps data transfer rate with my 6537 ?

[cc_file]

hello, everyone,
i am a Novice of NI products. my boss give me a NI 6537 and let me sampling 32 digit signals with a 50MHz external clock.
i write a simple demo code in vc2005 and it works at 25MHz clock, but when the clock freq is 50MHz, an error occured, the error message is something like -->"on board memory ... data transfer rate can't  ...the throughput of the card.  please  lower the freq of the clock..."
how can i do now.?  how can i reach the 200Mbps data transfer rate with my 6537 ?

thanks for reply !

btw. the procedure of my code is(sorry, the code is not at hand):

createtask
create DI channel, 32 signals in one channel
config simpling clock to continue simpling

for(condition)
{
    read raw data,
}



Message Edited by cc_file on 01-03-2008 05:27 AM

[Ryan_M]

CC

the 6536/7 is a streaming device.  that is, it does not have any onboard memory like the Ni 65xx devices.  What this means is that the hardware can only operate as fast as the system can stream data to/from it.  This operation is dependent on the type of computer the device is in, how many PCIe switches it must go through and how those interconnects are configured.

Here is a link to a document with some PXIexpress benchmarks including some 6537 results:
http://zone.ni.com/devzone/cda/tut/p/id/5897

Figure 6 and the comments after it show that the streaming performance in a PXIe chassis is dependent on the system configuration.  In one slot you can achieve a maximum 200MBps generation data rate but in another slot you cannot quite reach that throughput (179MBps).  This is due to the fact that the slots have different routing topologies that limit the maximum throughput.

If your 6537 is a PXIe device, NI can make recommendations on which slots and controllers and coding practices will give you the best performance (see the link provided).  In a PCIe system, you may have to contact the vendor to determine which peripheral slots will have the best performance.

[cc_file]

thank you for your quick reply.

my card is a PCIe-6537.  the card is  inserted in a PCIe 1x slot in my PC. 

can i infer from your reply that "if i  set the external clock to 50Mhz, i must ensure that the data transfer rate between 6537 and PC's memory > 200MB/s, or the error will occur." ?

[Ryan_M]

CC,

You are exactly correct.  The 6537 can push and pull data between the DUT and the system at 200MBps.  Whether the system can keep up, is a function of many different variables.  You should have consistent performance for a given system.  That is, if you test and find that in a given computer you are able to sustain 46MBps then it shouldn't change much with time or temperature.  It may change with load (ie if you put more cards in the system).  However, if you move the card into a different computer you may get better or worse results. 

Theoretically, a x1 PCIe slot can yield up to 250MBps of throughput.  When you take into account overhead of transactional content, lane sharing (ie switching), bridges, etc, this 250 number will drop.  We've put a lot of research into understanding these issues as we designed our PXIe platform to mitigate many of these problems.

This is all ignoring software.  The link I pointed you to mentioned various coding techniques to make sure you are getting the most out of your system.  If you do not fetch data efficiently then you could be artificially limiting your performance.  You may notice performance changes by increasing/decreasing the amount of data you fetch at a time. For small transfers this is less of an issue but for sustained operations, this becomes more critical.

[thehobbs]

Keep in mind that you can achieve continuous streaming of the max front end sampling rate on a smaller number of channels (8 or 16). The result is less data throughput required on the system.

[Ryan_M]

that's a good point.  You'll notice in that link that if you use 16channels, you only require 100MBps throughput.  The driver and hardware are smart enough to package the data such that you aren't sending 32 bits of data when you only need 16 (or 8).  However, you only gain this benefit if you can get by with <16channels (or <8channels for further optimization) and those channels are contained within ports.  that is, you wont gain any benefit if your 16 channels are DIO0-8 and DIO14-20 since this actually requires all four ports of the device.  The NI 6536/7 help file has much more detailed information on the port structure of the 6537:

http://digital.ni.com/manuals.nsf/websearch/E5E1DC8E66F8387886257209006D2399

[cc_file]

thanks for reply,

My project is to sampling signal with 100MHz clock, 14bit.  i decided to use PCIe-6537 so that i only need to develop A/D D/A module, and i use the PCIe-6537 because it can reach 200MB/s data rate.

i encouter another problem now.
        when i acquire .32bit counter data from the 32bit port with a 25MHz external clock.  the sampling data errors  Occasionally, this always happens  when the counter changes from 0xXXXXFFFF --> 0xXXXX0000.  So I check the sampling clock and find out that the waveform of the clock is bad at NI CB-2162 PFI5 pin. In NI CB-2162 terminal block, there is a 0 ohm resistor, i replace it with a 50 ohm one and the waveform is still bad.
my question is "when use a external clock with PFI5 line, what is the Electrical Properties requirement to the clock?".

[Ryan_M]

CC,

The 6537 is only capable of a 50MHz clock rate.  If you need to interface at 100MHz then I would suggest looking at the 6542 or the 6552.

Also, if you are capturing only 14bits of data, then you can gain the throughput benefits by selecting the correct pin mapping.  You should have no trouble sustaining a 50MHz interface rate with 14bits provided you keep the channels mapped to two ports.

In response to your questions, PFI5 is a source synchronous clock input.  The default populated 0ohm resistor is necessary since this is a series element.  It was made optional to allow users to replace it with a 50ohm series termination for those applications where the CB 2162 is used as a prototype platform and the driver is very near to the connector.  If you are cabling to the connector then you should leave it as 0ohms.

Futhermore, it is a synchronous datapath.  That is, the traces and cabling are matched between all of the data and pfi (clocks).  The 6537 does require some setup and hold time relative to the clock you are inputing to PFI 5.  These can be found on page 9 in the specifications:

http://digital.ni.com/manuals.nsf/websearch/906B148A0F455765862573690041C6BE

2ns of setup required
2ns of hold required

You can alternately use the data position attributes to sample the data on the falling edge of the clock.  This may provide sufficient margin to both setup and hold.

In regards to the "bad" waveform.  Keep in mind that if you have the 2162 connected up to the 6537, you will be probing in the middle of a transmission line so you will see a reflection.  Depending on the source impedance of your driver and the impedance of your interconnect to PFI 5, these reflections may persist.  the 2162 and the 6537 cable are designed for 50ohm matched impedance.  the interconnect and driver should match these characteristics.  If they are matched, then probing in the middle of a transmission line will show a stair step in your waveform.  Try running at some slow speed (5MHz) and let the reflections settle out.  The 2162 and cable have about a 5 to 6 ns propagation delay so you should see a step on the order of 11ns if you probe at the resistor on the 2162 (assuming your interconnect is well matched).  If your waveform is a departure from this, please attach a screenshot and a detailed explanation of your system interconnect.

[cc_file]

thanks again for your reply.

1)In regards to the "bad" waveform.  can i deduce from your reply that the wavwform i see is the waveform of the middle point of signal line, the waveform at the endpoint maybe OK ?

2) In regards to the figure "Acquisition Timing Diagram Using PFI 5 as the Sample Clock" on page 9 in the specifications, is the Trigger signal must exist ?  i do not set this signal in my VC demo program but the program works OK.

[Ryan_M]

CC

1)  It may be okay.  I can only speak generally since I don't have your measurements.  I have some materials I've compiled over the years attached below that show some real use cases comparing measurment techniques.  In each screenshot I am probing the exact same signal, just at different points in the cabling.  Some of the plots look awful until I probe at the receiver, which is all that really matters.  In your case, you can't probe at the receiver since it is on the 6537 so you'll have to make some assumptions based on what you are able to probe, which is why I mentioned how long the stair step should be, etc.

2)  Triggering is just a simple way to ensure determinism or to synchronize operations.  They are not necessary for any operation.  Triggers are bounded by the same timing requirements as data (setup and hold).


Message Edited by Ryan M on 01-04-2008 01:59 PM