internal clock digital start problem

[Adao]

Hello there,

I'm trying to acquire 6 channels (PCI 6036) triggered by digital signal(falling edge).For this I used the Acq&Graph Voltage-Int Clk-Dig Start.vi in the examples.

However when I try to put any processing in the while acquisition loop the samples come every 2 seconds. I'm assuming it does not have time to the calculations that I'm asking.

I find this strange because I had this same structure and calculations using continuous acquisition and it was able to do everything in 1 second.

I' attaching a picture of my vi. I want to know why this worked with continuous acquistion and does not work with this kind of triggered acquition and a solution for this problem.

Thank you,

Adam

[John_P1]

Hi Adam,

From your screenshot, it looks like you are starting and stopping the task every loop iteration--this can add significant overhead to the loop time. I recommend you look into the following KnowledgeBase article that has a bit more information about how to do retriggerable analog inputs:

How Can I Perform a Retriggerable Analog Acquisition

Essentially, the best way to do this is to use the on-board counters to generate a re-triggerable finite pulse train to use as your AI sample clock.  The shipping example mentioned in the above link should be a good starting point.  Note that generating a finite pulse train requires the use of both M series counters.

If this is not an option (i.e. you need to use the counters for something else), you could optimize the code slightly by committing the task outside the loop.  You can explicitly commit the task by calling the DAQmx Control Task function in LabVIEW.  This would reduce the overhead of stopping and restarting the task--when a DAQmx task is stopped it will return to the state that it was in before it was started.

-John