multiple sample rates, 9205/9068

[hshane]

I have a 9205 analog input module in a 9068 cRIO chassis. I understand that I must sample all the analog channels at a common rate. However, this means that the lower bandwidth channels will be highly oversampled in order to avoid aliasing of the higher bandwidth ones. Rather than flood our logging system with all this oversampled data, I would like to insert resampling filters in the lower bandwidth digital signal paths. It would be straightforward to do this in software but there will likely be performance limitations. Alternatively, is this something that can be implemented in the cRIO FPGA? I know that's the sort of thing the FPGA was intended for but it's not clear to me if I can implement channel-specific filters.

[scotia673]

At what rate are you going to be reading data?

[hshane]

I'm not sure I understand what you mean by "read". Suppose we sample all 32 channels at 5 ksamp/sec, which is well within the 9205's maximum aggregate sample rate of 250 ksamp/sec. Furthermore, suppose 4 of those channels have signal bandwidths of 2.5 kHz. In other words, we need all 5 ksamp/sec on those four channels. But the rest of the channels have signal bandwidths of only 25 Hz, so we only require 50 samp/sec on those channels. Then ideally, we would acquire 4 channels at 5 ksamp/sec directly and 28 channels processed by a bank of downsampling filters to 50 samp/sec. What I'm concerned about is whether or not the cRIO architecture allows this.

[scotia673]

Yes, this would be supported on the cRIO architecture, but not in scan mode (i.e. without using the FPGA) - the maximum acquisition rate in scan mode is 1kHz. But if you implemented this in FPGA code, you wouldn't need to downsample - you could have two parallel loops running at different rates (5 kHz and 50 Hz) reading from channels of your choosing.