Sorry for the delay. I tried to reply yesterday but due to indifference of some other individual the draft that I was writing got obliterated.
In my previous reply I first thought of asking you about some basic information on how U1's (the Analog-to-Digital Converter) control and status signals work because I don't have access to its specifications (I don't have Multisim application as I mentioned earlier). On the other hand, I deemed it will only cause additional delay in finding the solution to your problem. The Analog-To-Digital Converter in your circuit appeared fictitious with no real-world part number, only a generic name ADC. Initially, I thought of similarity of operation with National Semiconductor's (now part of Texas Instruments) ADC0800 except for the complemented logic state of the End Of Conversion status signal. The absence of clock input, however, discouraged me from closely relating the ADC in your circuit to the popular ADC0800. I then proceeded to assume that the active-low End Of Conversion (~EOC) signal goes low at the end of a conversion cycle and stays low until the succeeding rising edge of Start Of Conversion (SOC).
Thanks, but I am still not getting any output, and the not Q output of U9 is 5 volts all the time,
If my assumptions about the initial states of the circuit and ~EOC were correct, the circuit could have just performed one shifting cycle. This is because I mentioned that the SET input of D Flip-flop U9 should be connected to ground or to a valid logic 0 source. My assumptions were wrong.
I looked closely at the not EOC pulse coming out of the ADC and it is only 2 us wide I think if I can put a one shot on it with a long enough pulse to trigger U9 it will work.
The notion of using a monostable multivibrator is fine, it can solve the problem but let us try if we can find better alternative.
As I said the NOT EOC pulse is only 2 us wide.
This parameter reveals how the ADC operates and hopefully we can find an elegant scheme to make your circuit work. This width of ~EOC is narrow enough to be used as a one-shot trigger but I perceive this width as wide enough to be used as asynchronous SET or RESET input signal(s) to a flip-flop.
Here are my new recommendations, let us use the first image that you attached (ADC_Serial.PNG) because my modifications in the second image can introduce confusion.
- Modify the timing parameters of V1, the Start Of Conversion (SOC) generator, from 5 ms / 10 ms to 25 ms / 50 ms (this is just to make the circuit work, these can be adjusted later to more efficient values).
- Replace D Flip-flop U9 with another D Flip-flop but with active-low set and reset (~SET, ~RESET) type. This "new" Flip-flop is just for convenience, inverter(s) can be inserted in the original circuit as an alternative. For reference, the D Flip-flop in your original circuit is Type 1 and the replacement I recommend is Type 2 in this Multisim Live Help page. Based on this Help page, the Flip-flop need not actually be deleted and replaced, the original may just be configured.
- Connect the Q output of the D Flip-flop to the Shift/Load (SH/~LD) input of U5 (74166). This connection is thus similar to the original circuit.
- Connect the D input of the D Flip-flop to ground or to a valid logic 0 source (you may just connect them to U6 or U8 which are connected to the INH and SER input terminals of 74166).
- Disconnect the clock (CLK) input of the D Flip-flop from V4 and CLK input of U5 (74166). This should not affect the connection between V4 and CLK input of U5 (74166), they should still be directly connected.
- Connect the clock (CLK) input of the D Flip-flop to V1 (which is also connected to SOC input of ADC U1).
- Connect the active-low set (~SET) input of the D Flip-flop to the active-low End Of Conversion (~EOC) output of U1 (ADC).
- It is preferable to connect the active-low reset (~RESET) input terminal of the D Flip-flop to a valid logic 1 source (you may just connect it to U7 which is connected to the ~CLR input terminal of 74166).
