Hi Scott,
When I first saw your circuit I thought you are looking for a synchronous solution to your problem. This is because you have placed D Flip-flops which might be used later and the shift register you have chosen is 74166. The 74166 is a fully synchronous shift register.
The second solution that I proposed is not meant to solve timing hazards and metastability issues associated with the shift register. I just wanted to see if it will work smoothly in simulation. I'm just waiting if you will try that proposed circuit and if you will post the schematic diagram and simulation results. If you did, I planned to post some more possible solutions and the strength and weaknesses of each of them. Although I want to steer the discussion towards a synchronous solution and efficient timing parameters, we could have also considered alternatives.
The circuit that you posted and marked as a solution is clearly wrong.
Very carefully review your own explanation of how your circuit works. From that, it means that your serial interface must have additional Data Valid Status Signal. No absurd serial interface system like this exist. Serial data transfer systems contains only data, handshaking, control, and pertinent status lines not a data valid status line. You can search from the books in your library and dig on internet websites specially microelectronics/semiconductor device manufacturers to study UARTs, SPI, Microwire, I2C/TWI, etc. The proper behavior of the circuit is that it should serialize the data output of the ADC, when the last bit is shifted logic 0(s) should follow as defined by U8 which is driving the SER input of 74166. People who have real knowledge in this field will clearly see that you have a chaotic system because your serial data is not properly framed. The reason for this is that you did not pay proper timing consideration to ~EOC. Another problem that you have overlooked is that your circuit will shift unpredictable data in the first shifting operation, will shift stale data on subsequent shifting operation, and the supposedly last data may never be shifted.
I am not really sure what you are trying to accomplish but it seems like you want your circuit to start shifting exactly at the falling/rising edge of V1 and end shifting exactly at the rising/falling edge of V1. I want to inform you that the real-world solution would require additional components. If you are still interested in further broadening this discussion you can reply and state that this is indeed your intention. It will also help if you can provide waveforms showing SOC and ~EOC because the timing parameters for these signals are important.
Moreover, deeply and diligently study Serial Peripheral Interface (SPI) an industry standard for MCUs, data converters, and other ICs. From the detailed timing diagrams you will find that if MOSI/MISO is used as a framing line, the transitions will not coincide with the exact start and end of serial data stream. It has offsets or margins to give consideration to setup and hold times.
I would like to end my reply here because I don't have much time anymore. If I'm going to have free time in the next few days I might post possible real-world solutions and even circuits that can work in ideal world or simulation but have associated caveats if implemented in real circuit.
Best regards,
G. Goodwin
