Problem with Multisim: Async signal not support on 74ALS74AN?

[Jumbo.Lee]

A simple schematic to test 74ALS74AN.

Pin Q# is connect to pin D, and pin CLR# is control by a switch.

But the Logic of 7474 is wrong:

when J1 is on, CLR# is Lo, 7474 must be output Q=0,  but why Multisim report it like a Divider????

Similarly, when J1 is off, CLR# is high, 7474 must be output Q=D#(like a divider), why Multisim report output D=1.

Is it a bug with Mutlisim?

[OStep · Accepted solution]

Jumblo.Lee,

The asynchronous Reset (Clear) and Preset pins are active LOW in this component. Your Preset is left floating and is actually being interpreted as a LOW. So when J1 is closed, both Reset and Preset are active, a hazardous condition you want to avoid in Latch and Flip-Flip circuits. It turns that this component ignores these asynchronous pins under such a condition. Thus you see the normal clock divider output.

To fix the issue, just tie the Preset pin to a HIGH.

Regards,

Message Edited by MaxNI on 09-16-2009 09:21 AM

Message Edited by MaxNI on 09-16-2009 09:26 AM

[Jumbo.Lee]

I think 74 series IC's input pin is equivalent to the high when floating...

When I link Pin PR# to VCC, it's ok!

Thank you very much!