vhdl component

[max2mil5]

Hi

i want to create a vhdl based component and simulate it on a circuit with some analog devices for example (to test co simulation in multisim). i tried to read this tutorial for creating a simple 1 bit adc component => http://zone.ni.com/devzone/cda/tut/p/id/5653

and followed steps to simulate the created component but it does not work at all..when ading some analog component like power source to the circuit, i get errors like :

------ Checking SPICE netlist for Design1 - vendredi 9 mars 2012, 17:16:53 ------

Error message from simulation: ERROR - node $1 cannot be both analog and digital

Error message from simulation: EVTinit: Unknown error code

======= SPICE Netlist check completed, 0 error(s), 0 warning(s) =======

.......

i use multivhdl for creating the .vx file needed in component tool wizard

and multisim 12.0

note: in component tool wizard when multisim ask for the .vx file i try to browse and load the .vx file but i get a window saying "Spice model must be a text file", so i typed ".model cpld d_vhdl(vhdl_file="C:\......vx") in model data field and i did not use the button for importing the .vx file to bypass this error message

any tutorial for creating a vhdl based component and simulate it in multisim 12 will be great

[Mathieu_T]

Hi Max,

Did you read this one ?
http://zone.ni.com/devzone/cda/tut/p/id/6369

Regards,

[Techy813]

Using the component wizard in Multisim you can create a VHDL component in 9 steps. Select the "Simulation and PLD export" for this example name the component Full adder, the function is a high speed 4-bit fuller Adder IC with carry out feature.

Step 2

Step 3

Step 4

Step 5

Step 6

Step 7

Step 8

Step 9

To view model files and detailed reports, right click an existing component.

View component model

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