08-14-2014 03:46 PM
Drag the vertical black arrow left/right to move the cursor with your mouse. To move it with your keyboard type into the position, tooth, or offset controls.
I've found an issue adding pulses to the -360 to 0 degree range if you've added one to the 0 to 360 degree range. I'm looking into a fix now
08-18-2014 07:28 AM
Stephen, now i want to use 9263 and 9401 to generate engine camshaft and crankshaft signal, and get some questions to ask you:
1.do i have to create a Veristand FPGA project including 9263 and 9401 before adding a lvbitx file in this custom device? so how to create the Veristand
FPGA project ? is it created by FPGA-Based I/O tools as instructed at https://decibel.ni.com/content/docs/DOC-13815? if so, how do i create the
Veristand FPGA project related to this custome device because it doesn't include the old AES library vi at https://decibel.ni.com/content/docs/DOC-5684
2. Do the 9401 simulate both the camshaft and crankshaft signal using this custom device in session of digital patterns and 9263 simulate both them in session of Angle process unit?
3. my customer 's camshaft signal consists of 6+1 sinusoidal analogy waveform and crankshaft singal consists of 58+1 sinusoidal analogy waveform , so is it configurated in digital pattern session as below:
here is my custome cram and crank signal waveform pictures from sensors: the top one is crank signal, and the bottom is cram signal
so is it right for my configuration in VS?
looking forward your reply.thanks
08-18-2014 09:04 AM
Hi Jarm,
1. You will need to create a bitfile that suits the IO you need to do for your application. See my post #6 above for how to do this.
To create a bitfile:
- Download the vip file attached to the page.
- Install it with VI Package Manager 2014 or later
- After installing, click 'examples' to navigate to the examples provided with the VI package
- Open the examples to see how the FPGA IP is put together
- Use the information from the example to create your own bitfile for your specific needs on your specific FPGA target
2. The 9401 is a digital module, so it is used for digital pattern generation. The 9263 is an analog module so it is used for analog replay. Each can be used for crank and cam generation, depending on the sensor type... digital (hall effect) or analog (variable reluctance). See the description from the NI Engine Simulation Toolkit for NI VeriStand
Digital Pattern Generation
- Typical crank and cam Hall effect sensor simulation
- Generates arbitrary digital pulses based on engine position
- Intuitive, powerful GUI for pattern design
- Rotationally phase playback position at run time
Analog Replay
- Typical crank and cam variable reluctance sensor simulation
- Replays any data file over a crank or cycle rotation
- Scale voltage by engine speed or manually
- Rotationally phase playback position at run time
3. If your customers signal is a sinusoid analog waveform, you should not use digital patterns to simulate it. Instead, you should use analog replay.
08-19-2014 09:46 AM
why do the sys defenition file have nothing to configure after i build the lvbitx file?
I post the cRIO project as attachment
08-19-2014 10:53 AM
Hi Jarm,
Your FPGA code would have to include Engine Simulation Toolkit IP for it to have any Engine Simulation Toolkit IP in it.
08-20-2014 04:35 PM
NFT,
I've made a fix to digital pattern gen in the latest version I just posted. Can you give that a try and see if the GUI works better?
https://decibel.ni.com/content/docs/DOC-37304#121
08-21-2014 09:47 AM
Hi Stephen,
Much better. Thank you!
08-21-2014 09:55 AM
Fantastic. Thank you for getting back to me!
08-26-2014 04:10 PM
Hi Stephen,
I have some questions/comments about the "Select Analog Data Replay Data Options" window:
Thanks!
08-26-2014 06:14 PM
Hi NFT,
Thanks for the feedback