Scan Engine & EtherCAT Custom Device Feedback

[Sankar_Longhorn]

Hello All,

I am fairly new to Veristand. The version I currently use is 2012 SP1. I have a cRIO 9075 and two analog cards NI 9381 and NI 9205. Reading up online and with some help from NI tech support, I realized that I need to add a custom device - > Scan Engine & Ethercat in order to add/detect C series modules in Veristand. I was able to add the scan engine & ethercat custom device on my veristand. When I tried to auto-detect modules, it would not detect either of the C series modules. I tried to manually add them but I could add only the 9205 as the 9381 did not pop up on the list of devices. When I tried to deploy the application, it comes up with the error as shown below. Could someone guide me on what am I doing wrong ? I have also attached an image showing all software installed on my cRIO 9075.

Regards,

Sankar

"Preparing to deploy files to the targets...
• Starting download for target Project_cRIO_9075...
• Opening FTP session to IP 169.254.4.42...
• Processing Action on Deploy VIs...
• Setting target scan rate to 10000 (uSec)... Done.
• Gathering target dependency files...
• Downloading Project.nivssdf [71 kB] (file 1 of 3)
• Downloading Project_Project_cRIO_9075.nivsdat [144 kB] (file 2 of 3)
• Downloading CalibrationData.nivscal [0 kB] (file 3 of 3)
• Closing FTP session...
• Files successfully deployed to the targets.
• Starting deployment group 1...
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -1950678941 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  An empty string is not a valid URL.  If you want to reference the root container within a variable engine, you need to specify the path explicitly using one of the following URL formats: "[Variable Engine]://[Host Name]", "[Variable Engine]:", or "/".
=========================
NI VeriStand:  NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> HP Loop.lvlib:HP Loop Main.vi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Sending reset command to all targets...
• Unloading System Definition file...
• Connection with target Project_cRIO_9075 has been lost."

[Devin_K]

Hi Sankar,

A few things:

1) In order to auto-detect modules, you need to install the "I/O Variable Remote Configuration Web Service" to the CompactRIO.  You can install this from MAX (see picture below).  This is mentioned in the custom device readme file, but it's easy to miss, so I don't blame you for having this problem!

2)  Unfortunately the 9381 module is not currently supported in scan mode.  I know that RIO R&D plans to add support for it, but I'm not sure what the time-frame is yet.  When support is added, I'll add the module to the custom device for use in NI VeriStand.

3) I'm guessing you're using version 4.0.1 of the custom device, which had a bug in it which would cause deployment to fail if the system was not syncronized to the scan engine.  You should download version 4.03 here.  You should also be able to fix the problem by checking the "Synchronize NI VeriStand to Scan Engine" on the main page of the custom device.  Even if you upgrade to 4.03 you should check this box, since it will offer lower latency in your system.

[Sankar_Longhorn]

Hey Devin,

Thanks for the hint on #3. Checking that box had a successful deployment. Actually the version I have is 4.0.2. The deployment was successful this time on the target.

On #1, I do have the IO variable remote configuration installed on my cRIO (screenshot in the previous post). But autodetect would not work. Not sure why.

On #2, do you think I can write a labVIEW VI in the FPGA target for that card and import that into veristand as a separate model/custom device ?

Appreciate the help !

Regards,

Sankar

[Devin_K]

Yes, unfortunately until scan support is added, you'll need to write an FPGA personality to support your 9381.  You have a few options for this..  You can either use the built-in NI VeriStand FPGA support (see here for more info), or write a hybrid bitfile and import it into the scan engine custom device under the "User Variables" section.  If you write a hybrid bitfile, you'll need to expose all of the I/O with "User Defined Variables" in your LabVIEW project.  So you have a few options:

1) Use the 9205 in the scan engine custom device, and make a bitfile which exposes the 9381 channels using user-defined variables.

2) Write a bitfile using the NI VeriStand template which exposes the I/O for both the 9205 and the 9381.

3) Use the 9205 in the scan engine custom device, and write a bitfile using the NI Veristand template which exposes the 9381 I/O.

In my opinion, 1) is probably the easiest.

Also, note that 3) is only possible because you're using a 9075, which has 5 DMA channels (most of our FPGA targets only have 3).  The scan engine requires 2 DMA channels, and the NI VeriStand template requires 2 channels, so this approach wouldn't work with some of our other FPGA targets.

[Sankar_Longhorn]

Hello Devin,

Could you guide me a little bit on option 1. If I want to create a bit file just to expose the 9381 channels, what is the bare minimum I need to do ? I did one for XNET modules where all I did was to add the channels on to my chassis and create an empty VI to create the bit file. I tried the same and it did not work.

Looking at the Veristand template, I guess the 9381 might be a little more complex ?

Regards,

Sankar

[Devin_K]

Hi Sankar,

I have attached an example project I put together for the 9381.  It's basically the combination of two examples in the Example Finder:
"NI 9381 Advanced IO.lvproj"

"User-Defined IOV Synchronized.lvproj"

The basic steps for setting up one of these projects:

• Add your RT target to your project, its chassis, and its FPGA target
• Under the FPGA target, add any modules you will be programming in the FPGA
• Under the chassis, add modules for the remaining slots (the module type doesn't matter.  As long as there is a module for the slot, it will be configure for scan mode, and any module can be placed in it.  In my example they're set as 9201, but they will be able to accept your 9205)
• Under the chassis, create "User-Defined Variables" for all of the IO (and any other communication you may want).  Make sure the data type and direction of the UDV matches the IO.
• Make an FPGA VI and follow the examples to synchronize your loop to the scan engine.  Read/write your IO and pass the data to/from the UDVs.

In the attached example I have the 9381 in slot 1 of the chassis, so you may want to change that before compiling.  Also, I have the module set up so DIO0 and 1 are inputs, and DIO2 and 3 are outputs.  You can change this by going to the module properties in the project, then changing the IO node and UDV directions.  Or, you could get more complicated and have configurable direction for each line while running.  You can sort of follow the "NI 9381 Advanced IO.lvproj" example if you want to accomplish that, although you'll need to add more IOVs to the project to accomodate thath.

Hope that helps!

Devin

[Sankar_Longhorn]

Boy did that help ! Thanks Devin for doing that and sorry for the late response.

This is what I did :

1. I used your VI (untouched because the config matched my needs) and created a bit file. Is it OK to do that or should I have to modify it ?
2. I uploaded the bit file on to my veristand config file and it seemed to accept it alright. I saw slot 1 became unavailable (allocated for 9381). In slot 2, I changed to 9205. I did my mappings and it did not show any errors or warnings.
3. When I try to load the veristand application on to my cRIO, I get the following error message. Could you please comment on what am I missing ? 

"

Details:

Error 1124 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  VI is not loadable.

In a built application, this error might occur because the VI being loaded was last compiled for a different OS or with CPU features, such as SSE, that this target does not support.

In this case you must rebuild the application for the target OS and make sure SSE compiler settings in the build specifications match the target platform. This error also might occur

if the VI is a polymorphic VI, which cannot be loaded in the LabVIEW Run-Time Engine. You must load an instance of the polymorphic VI instead of the polymorphic VI itself "

Thanks,

Sankar

[Devin_K]

Hi Sankar,

Are you sure you have the right operating system specified for your target?  Go to the "Controller" page in the System Explorer, and make sure "Operating System" is set to VxWorks and the IP address for your system is correct.

If that's all correct, does the problem only occur when you have the scan engine custom device in your project?  Does it still happen if you don't have the FPGA loaded in the custom device?

Regards,

Devin

[Sankar_Longhorn]

Hi Devin,

Yes, the problem occurs only when I have the FPGA configuration loaded on to my user variables in Scan Engine Custom Device. I can confirm that. Please find attached the screen shot of my cRIO config page. This is without the bit file loaded. This

deploys successfully without any issues.

Thanks,

Sankar

[Devin_K]

It may be a problem with the LabVIEW version you used to compile your bitfile.  In general the LabVIEW version year must match up with the NI VeriStand version year.  So for NIVS 2012 you need to use LV 2012.  This isn't always a problem for bitfiles, but the format does sometimes change between versions, so it's a potential culprit.  Did you compile your bitfile with LV 2011 or 2013?  Are you able to compile it with 2012 (assuming you're using NIVS 2012)?