Scan Engine & EtherCAT Custom Device Feedback

[NFT]

Actually, it appears that there were two separate issues. When I attempted to deploy to the cRIO-9014 on my development PC after resolving the NI-RIO IO Scan discrepancy, the deployment timed out without getting the RT Driver VI error. Communication to the cRIO was completely lost until the target was rebooted.

I'm guessing this is the result of the cRIO running out of memory:

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The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -307672 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

NI VeriStand:  One or more targets failed to start within the specified timeout. Verify that any start trigger or clock signals are configured correctly.
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NI VeriStand:  NI VeriStand Gateway.lvlib:VeriStand Server Wrapper.vi >> NI VeriStand Server.lvlib:NI VeriStand Server.vi

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Thanks for your help, everyone!

[Jiri_K]

Hi NFT,

unfortunaly this message typically means, that RT engine stop responding on the target...

~Jiri

[NFT]

Yes, I realized that. I figured it was due to the target running out of memory. I've since replaced that target with a cRIO-9024 and the error has gone away.

Thanks again.

[Ryan_S]

Hey Sebo,

After revisiting my tests, you are correct that the 9401/2 does also cause a DECOM fault if the specialty digital setting is set to anything other than none. So, if you need functionality offered by the specialty digital setting, you'll need to pull the module down to the FPGA. I've updated the known issues list of the custom device to reflect the behavior with the 9401/2.

As for how to pull the module down to the FPGA, you are correct, you will move it down under the FPGA target in your LV project. Then you'll write code under the FPGA target to perform the digital logic you need and send that data up/down to VeriStand using User-Defined Variables (UDVs). Hope that helps!

--Ryan_S

[emallett]

I need some guidance regarding NI-9144 chassis with custom FPGA files and the Scan Engine and EtherCAT custom device. I am using LabVIEW 2011 and Veristand 2011 with the latest version of the Scan Engine and EtherCAT device. Hardware consists of an cRIO-9082 with 3 NI-9144 chassis. The 9082 has a FPGA file which I access with a custom device, the resource name and and FPGA reference.

I have the bit file for each NI-9144. However, no resouce name can be assigned so accessing the FPGA with a custom device and a FPGA reference doesn't appear possible. When selecting the bit file in Veristand for each slave in the User Variables tree item no channels show up in the tree. Best I can tell I need to generate an XML file to have the channels available. Unfortunately, I can find no information to accomplish this with 2011 software versions.

Any guidance is greatly appreciated!

[Thør]

Fortuantely with the 9144, and in general with the Scan Engine/EtherCAT custom device, there's no need for any kind of XML file to get your I/O to show up.  Instead, you must create I/O Variables under the target, and they will automatically populate when you select the bitfile in the "User Variables" section.  If you're not familiar, you can create these User-Defined Variables (UDVs) by right-clicking on the chassis in your LabVIEW project, and selecting New >> User-Defined Variable.  UDVs have a direction, either FPGA to Host or Host to FPGA, and the direction you select here will affect whether VeriStand imports it as an input or an output.

In short, if you have no UDVs under the chassis in your LVFPGA project, you won't have anything populate under the User Variables section when you import the bitfile.

Fun tip, with this custom device you can use some modules in scan mode, and others in FPGA mode all in the same chassis.  Simply add dummy 9201 (or any) modules to your unused slots under the controller section in the LV project when you compile, and the scan engine EtherCAT custom device will allow those slots to be auto-detected and used in scan mode.

Hope this helps!

-Kyle

[JohnBergmans]

I'm using a NI 9214 thermocouple module with VeriStand 2013.  In the Timing Modes section of the 9214 Operating Instructions document (p.22), there is a note stating that "Sampling faster than the maximum sample rate may result in the degradation of accuracy." 

In my application, the Primary Control Loop has a Target Rate of 1 kHz, which is considerably faster than the 68 S/s Sample Rate of the "High-speed" Timing mode for this module.

A few questions:

1. How does the Scan Engine and EtherCAT sample data from the 9214?
2. Does the the Scan Engine and EtherCAT sample data from the 9214 in a way that would degrade the accuracy of the 9214 at a PCL rate of 1 kHz and if so, what level of degradation could I expect under these conditions?
3. More generally, is there any documentation available for the configuration pages of the supported cRIO modules?  Ideally, it would be great to have a "Help" button on the configuration pages, but this doesn't exist.

Thanks for any insights or help that you can provide.

-John B

[rdkroupa]

I am having an issue with the 9411 module in the 9082 chassis while using the scan engine in Veristand.  When the module is set to a frequency measurement the resolution is degraded.  For example when measuring a 0.5-9.5 GPM flow meter it may only show steps of 0.25 GPM.  This issue goes away when doing a period measurment and converting the frequencies to microseconds.  Although when doing the period measurment other issues are introduced.  When the program is deployed the output will read the max value of the scaling factor until it reads a pulse. 

Has anybody else had these issues when measuring a frequncy using the 9082?

Ryan

[joshe]

Hi Rdkroupa,

I have had issues with the 9411 and the 9082 using the scan engine.  I found that the 9411 was only sampling at the loop rate of the RT, in my case 1000hz.  This caused me to miss pulses using a quadrature encoder setup.  I had to write custom FPGA code for the 9411 to use the quadrature and do a mixed deployment (9411 using FPGA code, the rest of the cards using the scan engine).  If you look back in the posts you will see some comments from me about it.  You would think that the 9411 would run at its own rate, but it doesnt' seem to in my experience. 

[russellb]

I am trying to deploy the systems definition file that references a Scan Engine & EtherCAT Custom device and I am getting error 7 shown below.  This same VeriStand project deployed in the past.  All I did was recompile the same FPGA VI and downloaded the bitfile before I got this error. I have looked at the forum and tried to delete ni-rt/config folder and also tried to clear and download the bitfile again. I have also tried creating a new VeriStand project file and autodetecting the modules and nothing seems to fix the issue.

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:

Error 7 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.

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NI-488:  Nonexistent GPIB interface.

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NI VeriStand:  NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> NI VeriStand Engine.lvlib:Initialize Inline Custom Devices.vi >> Custom Devices Storage.lvlib:Initialize Device (HW Interface).vi