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PXIe_CLK100 buffering

In the PXI-5 HW spec, Pg 66 it states as a RULE that each peripheral slot's PXIe_CLK100 shal be driven by an independant LVPECL driver. Does this mean that each clock should be driven by its own 1:1 LVPECL buffer or is it ok to use a 1:n LVPECL driver for n slots?
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Hey EggHead,
 
I had a quick question. I wasn't able to understand which PXI device you were trying to mention? Most of our chassis begin with a 10xx such as the 1042. Would it be possible to copy a link to the manual your mentioning as-well?
 
Thanks,
 
Nick D.
 
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Hi EggHead,

Questions concerning the PXI specifications should be directed at the PXI Systems Alliance (PXISA).  You can e-mail your questions to info@pxisa.org.

-Thanks

Spencer

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thank you
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