Trigger 5154 Scope Card with RTSI 0

[bmann2000]

I'd like to Trigger my PXI-5154 Scope Card using RTSI 0. I generate the trigger from a PXI-7842 FPGA card by writing to PXI_Trig0. The Trigger reaches the 5154 card, but the exact moment of the Trigger appears to vary between pulses by around 10 sample periods (1GHz sampling, 10kHz pulse being sampled). What is introducing this jitter into the measurement and how do I fix it? VIs with data set as default attached.

    

Jitter when using Trigger BNC on front of card:

[bmann2000]

I'll give you a little more detail.  The 7842 card is generating a pulse of 4-ticks duration (0.1uS), this is output via DIO0 and connected to CH0 of the 5154 card via the BNC on the front.  A Trigger pulse of 4-ticks duration is also generated by the 7842 card and output to both PXI_Trig0 and DIO3, this trigger pulse occurs at the same clock cycle as the measured pulse, they are both generated using the same single-cycle loop on the 7842.

The 5154 card captures the pulse, sample rate 1GHz, sample size 300 points (0.3uS).  On the .jpg graphs in my last post you can see only samples 119-136, but the full data set is included in the attached VIs.  What you see is the rising edge of each pulse, low time is blue transitioning to high time orange.  The .jpg displays 55 pulses, but again the full data set is in the attached VIs.  The 4-ticks duration pulse from the FPGA appears as 100 samples wide when sampled at 1GHz.

When I use the external BNC trigger on the 5154 there is almost no jitter.  When I change the code to use the PXI_Trig0, there is significant jitter.  Can you please explain why the Jitter is present when using the PXI_Trig0 and advise on a solution or workaround.

[gt3000]

Hi bmann2000,

 I would like to provide some further assistance via the forums.  Some further information is needed to evaluate the specification of the cards against the application requirement.

1. Which PXI chassis is being used?
2. Is the PXI-5154 card operating with Time Interleaved Sampling (TIS) enabled?
3. Which slots in the chassis are used for the PXI-7842 and the PXI-5154?
4. Which version of NI-Scope and NI-RIO are installed? 
5. What is the source of the External Trigger when it is used?
6. What is the rate of the clock source being used on the PXI-7842?

Following the previous post, can you confirm that the graphs are trying to show approximately 10ns of jitter?

Regards, 

[bmann2000]

Hi,

1. Chassis PXI-1031DC with solid state HD, 4 slots.

2. TIS not enabled (unless enabled is the default) I've not read up on TIS yet, but I would eventually like to sample at 2GHz.

3. Slot2 7842, Slot3 5154, Slot4 empty.

4. NI-SCOPE 3.5.2, NI-RIO 3.2, LabVIEW 2009.

5. Source of EXT TRIG is also 7842 DIO3, connected via a SCB-68 breakout box.  Note in FPGA code the same boolean connects to PXI_TRIG0 and DIO3.

6. 40MHz clock selected on fpga of 7842.

Graphs show at least 7nS of Jitter for Trigger routed via RTSI0.

The Trigger pulse generated by the 7842 is actually 20-Ticks wide, not 4 as previously stated.  More of 7842 code attached as .jpg, had to remove lots of notes.

As far as I can tell, in the experimental setup, I have exactly the same trigger routed to both the front and rear of the 5154 card.  The hardware and cabling is already built, we assumed the TRIG could be routed via the PXI backplane, so using the BNC on the front as a workaround would cause us significant rework.

[gt3000]

Hello bmann2000,

Thank you for the detailed reply.  The answers below helped in the following way:

1. Both card are part of the same PCI bridge in a four slot controller, which means the trigger does not have to wait in a queue for PCI bridge access.
2. TIS is disabled by default, and should not be needed at 1GHz.
3. This confirms no other noisy card is in between the cards in question.
4. Confirmed that there are no RTSI related bugs for these driver versions.
5. Confirms that the source is the same, clarifying how controlled your experiment is.
6. Clock signal with further explanation clarifies some questions I had about the code setup.

The NI 5153/5154 Specifications found online shows the Trigger Specifications on page 15.  The External Trigger is defined as an Analog Trigger.  The PXI_Trig and RTSI lines are defined as a Digital Trigger.  The Analog and Digital Trigger sections of the board will most likely have different components in place.  I am not able to confirm yet whether the Digital Trigger section has some prebuilt filtering which would cause a delay.  However, if that is the case, a Property Node of NI Scope may allow this delay to be switched off.

The front of PXI 5154 also has channels PFI0 and PFI1, which can act as digital triggers.  What jitter is seen if using these lines as a trigger?

Regards, 

[gt3000]

Just a follow-up, the following is a schematic of the PXI-5154 layout:

 

[bmann2000]

Hi,

If I can find cables to make the SMB connection I'll try it out.  When I first seen this problem the only reason I could think of was some type of multiplexing taking place on the card.  Now I've seen the diagram, is it possible for you to find out the detail on what circuits comprise the signal routing matrix?  RTSI 0-6 shares the same line of the diagram, we're seeing 7 samples of jitter.

[gt3000]

Hi bmann2000,

Understanding the internal working of the Routing Matrix is my primary focus, as well as any programmatic control its function.

I will post back as soon I have found supporting documentation.

Regards, 

[gt3000]

Hello bmann2000,

Have you been able to test with the external PFI lines?  If you have not been able to find SMA cables, we can test different lines.

From my research, I can verify that the Routing Matrix is an actual matrix, and not a multiplexing system.  A multiplexer would go through all the channels in sequence, as mentioned earlier, however, a matrix is actually a point to point route.  The length of that route should always be the same and not cause jitter.

In terms of testing the quality of signaling from one card to the other through the PXI bus, another trigger line can be used.  A PXI can reserve slot 2 as the 'Star Trigger'.  The 'Star Trigger' platform has a different bandwidth than the standard PXI_Trig lines.  Please move the R-Series card to slot 2, and have the digital line output on the FPGA code write to the Star Trigger.  The NI-SCOPE Configure Trigger VI can be modified to read from the Star Trigger as well.  The location of the PXI-5154 does not matter when use the Star Trigger, as it is designed to have the exact same length of PCB track between slot 2 and every other slot on the backplane.

The above test will show whether the issue is related to the Routing Matrix, or narrow it down to the PXI_Trig lines. 

Regards, 

[bmann2000]

Hi,

I found a SMB to BNC cable, about to try it out now.  I'll move the card and try out slot2 also. 

Brian