pxi trig problem

[Julien_BERNU]

Dear all,

I have trouble in synchronizing 2 FPGA's. I want to control which one is the master (producing the trigger signal) and which one is the slave.

I've been facing a strange problem that I've isolated in a simple program, see the attached project.

This program adds 1 to a number on each FPGA when the trigger is clicked on the RT. In the bugged version (FPGA) everything works well until the user swaps master and slave. After this only the master sees the PXI TRIG. I don't understand why.

The only way I've found to get around it is using multiple PXI TRIG (non-bugged FPGA version) but I still don't understand why this works better and it is not a satisfying solution in terms of scalability.

If anyone can explain me what happens this would be great!

Cheers,

Julien

[Ben_S]

Julien,

The only differences in the two codes that I see is that you are using a Numeric Control for a case structure in the "FPGA_Test.vi" to access the multiple trigger lines. In that case structure you have a flat sequence structure where you write to the TRIG1 line and then immediately read from it, this is not in your "FPGA_Test_Bug.vi" what is the purpose of that section of code?

When you are using the "Non-Bugged" version, how do you operate it such that you don't have the same behaviour that the "Bugged" version has. Also, when you are using the"Bugged" version, what is your order of operation when running the code?

[reddog · Accepted solution]

You're probably getting into a state where you're double driving the line.  If you're going to programmatically change who the master is going to be, you should really use the Set Output Enable method to tristate (stop driving) the line on the previous master before driving the same line on the new master.  The following link should provide a little more detail on how to use these methods.

[Julien_BERNU]

Thanks for your answers. The Set Output Enable method seems to be the solution. It works well now!