5640R users can try a new model of computation

[thayles]

I have just posted a new version of the Graphical Timing Software package to NI-Labs (http://www.ni.com/labs/). This package offers support for the PCI-5640R (as well as R Series and most cRIO products) and a different approach to writing LabVIEW applications. Specifially for the PCI-5640R are three free-running nodes that model the clock distribution circuitry (including the CDC7005), the ADCs and the DACs. In addition to consuming normal LabVIEW dataflow wires (for one time static configuration), these nodes produce and consume timing and data information on non-dataflow, asynchronous wires.

This package replaces the host side approach to programming the card. The 5640R is instead completely configured from the fpga target VI. The host VI uses only the nodes in the FPGA Host Interface palette like any other R Series or cRIO host VI.

If you have another project coming up that uses the 5640R I encourage you to download and try out this new programming model.

Thank you.

- Tim Hayles

[jaas]

is it possible to generate a sine wave from FPGA VI.if possible how can we program for it.please help

[thayles]

> is it possible to generate a sine wave from FPGA VI.if possible how can we program for it.please help.

If you want to generate the sine wave from the output channel of the 5640/1R you could use the Single Tone Mode of the DAC. There is an example project called ni5640R Single Tone Output in LabVIEW 2010\examples\instr\ni5640R\FPGA\PCI-5640R\ to get you started. This does not use the fpga however.

If you want the fpga to create the bits that describe the sine wave yourself, there is a VI on the LV FPGA palette that will do this for you. Look in Programming->FPGA Math & Analysis->Generation. Place this VI in a loop and connect its output to the input of an IO node bound to an analog output channel.

[jaas]

thx hayles,

               currently am doing a project AM Modulation using this 5640r.i am trying to modulate two signals from HOST VI and transfer this to FPGA VI.

     from normal VI this modulation result is getting.how can i transfer this modulated wave(from HOST  to FPGA(analog out)).actually i dont understand the example pgm(single tone output),from where this sine wave is generating and where the transfer part.

                                                               kindly please help me

[jaas]

hello hayles

                 i already placed the sine generator in the FPGA VI,here intermediate files are generating but code compilation is not taking place.if i can program like this simply i can do the modulation part which is my project.help me

[thayles]

The Single Tone example uses a feature of the DAC itself on the 5640R to generate the sine wave. There is no programmatic creation of the sine wave nor any data transfer. So it does not seem like a useful example for you.

To transfer data from the host to the fpga use a DMA FIFO. You can create the FIFO from the project window by right-clicking on the FPGA target, selecting new fifo and changing the type of the fifo to Host - to - target DMA (to move data from host to target). You use a method node on the host to write data and a second method node to read the data on the target. There is an example at <LabVIEW>\examples\R Series\FPGA Fundamentals\DMA\Basic DMA Output\ that shows how to do this. This example does not use the 5640R but the technique is the same.

Another example that might help is <LabVIEW>\examples\instr\ni5640R\FPGA\PCI-5640R\ni5640R Analog Input and Output\. Look at the generation loop on the fpga vi. It uses a local fifo but the code would be the same were it a dma fifo.

I am not an expert on AM modulation. Also, I cannot tell if you are modulating the data on the host (and simply writing it to the DAC on the device) or modulating the data on the fpga.

[jaas]

hello thayles

                        i created one program for sine wave generation(not the sine tone generator example).when compiling it generates intermediate files and code generation is also happening(now FPGA VI is running).then i run the HOST VI,its also running but i did not get the output on CRO.i attached the programs i did,please check and help me.

[thayles]

If the product you are using were a 783x R Series board, your program would be very close to perfect. You are using the DMA FIFO correclty. However, the 5640R product requires additional code to configure and operate it. I receommend you start with the PCI-5640R example Analog Input and Output (<LabVIEW>\examples\instr\ni5640R\FPGA\PCI-5640R\ni5640R Analog Input and Output\). It is more compilcated than you need, but you can strip out all the input related code. To use this example as a starting point for an application, refer to the "Creating an FPGA Application>>Using the ni5640R Template" section in the NI-5640R Getting Started Guide, accessible at: Start>>Programs>>National Instruments>>NI-5640R>>Documentation. Here are a few key things you are missing:

1. If you open the diagram of the FPGA VI in the example project (ni5640R Analog Input and Output (FPGA).vi), look in the upper left of the diagram for a Single Cycle Timed Loop named Configuration Timed Loop. You must have this loop in your FPGA VI and the controls and indicators inside this loop must be present on your VI as well.

2. If you scroll down to the lower right of that same diagram you will find a Single Cycle Timed Loop called the Generation Loop. The key thing to notice here is that a 16 bit I value and a 16 bit Q value are written to the (14 bit) DAC on alternate cycles of the loop. For your sine wave, your Q data can be all zeroes I think.

3. If you open the diagram of the Host VI in this project (ni5640R Analog Input and Output (HOST).vi), you will see a number of subVIs with green banners and 5640R inside them. These are the host configuration VIs for the 5640R and they must be run to get the 5640R ready for work.

Good Luck