FPGA 7961R and 5761R Digitizer for high speed triggered acquisition

[Jordi.Bach]

Hi Badri and thanks for the code, I'll test it right now.

To check if the graphical part of the host VI is responsible of the overflow issue, I deleted

the graphical plot. However, the results are quite similar with or without it. Beyond 40 KS

there's a overflow and the host is unable to read all the samples between triggers.

Anyway, I'll switch to the 2 & 4 channels versions because these are the ones I really

need implement.

[Jordi.Bach]

Hi again Badri,

After some days of trial and error, I've finally managed to obtain a working solution (+10KS/ch x 4 channels) using two fifos.

So thank you so much for your collaboration!

Regards,

Jordi

PS: if you want the project just ask me and I'll send it to you.

[Badri15]

Kudos for getting the project working.

[Jordi.Bach]

I already gave you some in the previous page, please check it