FPGA I/O single-cycle timed loop problems

[Neil.Pate]

Hi there,

I am getting a compilation error I do not understand.

I have a sub-VI with a single-cycle timed loop to do some bit bashing of a comms protocol using several of the digital output ports (using FlexRIO board). This compiles fine, but as soon as I try and set these digital output lines OUTSIDE the SCTL I get code generation errors on the compile. The error message is "Multiple objects are requesting access to a resource through a resource interface from both inside and outside the single-cycle Timed Loop, which is not supported."

The setting of the digital outputs outside the loop are not occuring in parallel, they happen before the SCTL. Why does this lead to a resource problem? Surely this is quite a common use case?

Is there a way around this, short of removing the SCTL?

Another thing that confuses me is that the SPI example from the IPnet pages has essentially the same (apparently not allowed!) architecture, how is this possible?

Thanks

Neil

[Mark_SAI]

Hi Neil,

I took at look at the SPI example from the IPnet, and I cannot see where the FPGA IO is being accessed from both inside and outside a SCTL, could you point it out to me?

You may want to try changing some of the advanced I/O properties, in particular to allow arbitration:

http://zone.ni.com/reference/en-XX/help/371599B-01/lvfpgadialog/fpga_io_advcodegen_db/

It may simply be a case of what it says on the tin: LVFPGA doesn't support what you are trying to do, and a different approach is needed.

Any comments welcome!

[Mark_SAI]

Just to follow up with a useful link:

http://digital.ni.com/public.nsf/allkb/23C996B86D079AFA86257117005906CF?OpenDocument

[Neil.Pate]

Mark,

In the SPI example the IO is accessed directly in the main FPGA VI (FPGA_Top_Level_cRIO_Main.vi) in the third frame of the sequence, and also inside Example_Port Code_cRIO.vi

Changing the arbitration properties does not seem to help.

I am considering changing my VI that has the SCTL to somehow include a state that does the initial configuration I want.

What bothers me is that surely this is a very common thing: I need to set the state of the port pins initially, and then talk to them inside the SCTL.  

[jhandy]

I apologize for resurecting an old post but I just ran into the exact same problem.  I am creating an SPI interface based off the SPI example and I am getting the exact same error.

Was there ever a resolution to this issue?

[Mark_SAI]

Hi,

Could you try doing all port I/O inside SCTL's. For instance, if you only need to set the state of the pins in an initialisation stage, wrap that code (or IO Nodes anyhow) in a SCTL with the stop terminal wired to a true constant (so it only runs once). This should have the affect of making all port I/O run in the same clock domain.

[jhandy]

That does the trick!  I knew there had to be a simple solution that I just wasnt getting.  Thanks Mark B!  Is there a way for me to "mark as solution" even though I didn't create this thread?

[Mark_SAI]

I'm afraid not, but thanks for your feedback. I can't believe this simple solution didn't occur to me 10 months ago... the benefit of experience 10 months later is always a nice thing to have!

[Ashwin85]

Hi ,

I tried running Same SPI example on my PXI -7852R and it gives me error as in attachment. can any one help resolving this.

Thanks,

Ashwin

[alcava.cr]

Hi there, I found a similar issue and provided a workaround. Check this thread and see if it applies to your case. I hope this helps.