Rif.: Generate a 32Mhz clock on a DIO pin of sbRIO9602

[Mariano76]

Hi all,

i wonder if it is possible to generate a clock signal of 32Mhz on 1 of the 50 pin of sbRIO 9602 P4 connector and in which way i can achieve this.

Is this generated clock reliable also in terms of jitter or overall quality?

Thanks in advance.

MR

[Cla_Cup]

Hi Mariano,

you can try to derive a new clock on your FPGA target by right clicking in the project explorer on the 40 MHz Onboard Clock and selecting new derived clock. In the configuration wizard you'll be able to declare a new derived time base to use in a Single Cycle Timed Loop in FPGA VI.

By using a SCTL you'll be able to set new derived clock as loop period. There'll be a jitter in the order of nano seconds, that could be a good compromise.

Best Regards.

Claudio Cupini

NI ITALY AE Dept.

[Mariano76]

Hello,

can you please tell me if this is this a correct way to generate a clock of 10 Mhz with sbRIO 9602?

Thanks

[Cla_Cup]

Hi Mariano,

yes, that is the correct way. But you have to change the clock. In your code you selected the 20 MHz clk. You can derive a new timebase by right clicking on the 40 MHz Onboard Clock in the project explorer and selecting New FPGA Derived Clock, in order to create a new derived timebase (10 MHz).

Best Regards

Cla Cup